Hello,
If the MMC0 does not used, could you provide the recommended pin treatment?
MMC0_CALPAD
MMC0_CLK / MMC0_CMD / MMC_DS: PD? left unconnected?
MMC0_DAT0/1/2/3/4/5/6/7 : left unconnected?
Regards,
Takeo
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[DRA829] MMC pins treatment if non used.
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CCS/TMS320C6678: Ethernet Initialization on more than one core
Part Number: TMS320C6678
Tool/software: Code Composer Studio
Dear,
I have a query regarding the ethernet on C6678
1. We have tried Ethernet initialization i.e., QMSS, CPPI, PASS, SGMII, SERDES config, Network initialization on Core0 and Creating socket on Core1, But it is failed at fdOpenSession( TaskSelf());
2. Changed NIMU driver for supporting all the cores and Tested Ethernet Initialization and communication on same core, With single core at a time, it is working fine
3. We want to use Ethernet on more than one core simultaneously, Is it possible and If possible can you please explain us how
Thanks & Regards,
Mounika Reddy
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AM5728: PCIe configuration in GEN1 mode
Part Number: AM5728
Hi
we are working with PCIe subsystem in our application. Is it possible to configure the PCIe SS1 and SS2 in Gen1 mode ?. what is the procedure?
Best regards.
Marka reddy
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[TDA4M] Is the 32K timer mandatory for TDA4M?
Hi,
Customer wants to know whether the 32K crystal (connected to TDA4M pad N28/N26) is necessary or not.
And what are the use cases we can imagine for this 32K timer?
Thanks.
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AM3359: EtherCAT Slave customization
Part Number: AM3359
Hello, TI Experts,
Our customer sent us questions about TMDSICE3359.
They bought TMDSICE3359.
And they tried to use TMDSICE3359 as EtherCAT slave with pre -installed EtherCAT program on SPI-Flash
by connecting their EtherCAT Master product.
Now they also want to modify the pre-installed EtherCAT program on SPI-Flash for their future product devlopment.
And we found related below wiki site.
http://software-dl.ti.com/processor-industrial-sw/esd/docs/indsw/EtherCAT_Slave/EtherCAT_Slave.html
Our trial seems to be success like below procedure;
1: We can modify SBL like below procedure:
- edit sbl_main.c and related source code files.
- gmake -s bootloader PLATFORM=am335x-evm SOC=am335x CONSOLE=UART BUILDCFG=boot BOOTMODE=mcspi
on "C:\ti\pdk_am335x_1_0_14\packages\ti\starterware"
- load generated "bootloader_boot_mcspi_a8host_debug_ti.bin" to SPI-Flash by using spi_flash_writer_AM335X.out
2:We can recover pre-installed EtherCAT program like below procedure:
- download PRU-ICSS-ETHERCAT-SLAVE from below site & installe to PC
http://software-dl.ti.com/processor-industrial-sw/esd/PRU_ICSS_EtherCAT_Slave/latest/index_FDS.html
- projectCreate.bat AM335x arm ethercat_slave_demo
on "cd c:\ti\PRU-ICSS-EtherCAT_Slave_xx.xx.xx.xx\protocols\ethercat_slave\projects"
- build generated project by CCS
- load below converted app_ti.bin file to SPI-Flash by using spi_flash_writer_AM335X.out
"tiimage.exe 0x80000000 NONE ethercat_slave_demo_AM335x_arm.bin app_ti.bin"
Then we can found the "some message" in the small display on the EVM.
Questions:
1: Is this procedure correct to recover the pre-installed EtherCAT program on SPI-Flash on TMDSICE3359?
2: Could you tell us the recommended way of "faster SPI-Flash writing method" for their mass-production product
other than using spi_flash_writer_AM335X.out by CCS？
3: We didn't find any message in "UART console" such as teraterm from SPI-boot.
But we found the proper message like below by load "bootloader_boot_mcspi_a8host_debug.out" & running by CCS.
Could you tell us how to realize proper "UART console message" from SPI-boot?
We would also attach our binary files like below;
We would appreciate if you check the SPI-boot behavior with your EVM(TMDSICE3359).
Best regards,
--
(Please visit the site to view this file)
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TMS320C6657: Several questions about Timer, Reset, Boot Mode and so on.
Part Number: TMS320C6657
Hi E2E team.
This is Jonathan from Avnet.
One of our customers is developing image processing board based on TI's TMS320C6657 DSP.
The customer is reviewing H/W design but they have little experience in DSP field.
Unfortunately, I don't have much experience in this field. So the customer is asking for some help from TI's expert.
I would appreciate it if you could review customer's questions and then answer those questions.
Thanks.
1. About Timer with TMS320C6657 EVM
Q1-1 : When we look at the TMS320C6657 EVM, It seems to me that DSP_TIMI[0:1] take input 24Mhz clock from the FPGA. Is it reference clock for DSP Timer?
Q1-2 : What is mandatory input clock to use DSP Internal Timer? Is it possible to use of external OSC instead of FPGA?
Q1-3 : What is the purpose of DSP_TIMO[0:1] in the EVM ?
2. About Reset operation with TMS320C6657 EVM.
Q2-1 : We don't want to use FPGA for RESET#, POR#, RESETFULL# signal. Could you let me know how to control those signal in what signal?
Q2-2 : Could you recommend the best way to control the RESET# signal without using FPGA?
3. About Parallel NOR Flash Boot form EMIF16
Q3-1 : We don't want to use IBL. In this case, as far as we are aware, we should revise built-in ROM boot-loader. Could you let me know what S/W changes must be made in this case?
Q3-2 : There are several chip select (CS0~CS5) for external device. Which one should I use for NOR Flash Boot?
Q3-3 : As far as we are aware, the I2C EEPROM is used to IBL-Booting in TMS320C6657 EVM. What data(information) does EEPROM have?
Q3-4 : If we are designing as IBL booting, do we have to configure Boot Device to I2C Master?
4. About Configuration bootmode with TMS320C6657 EVM
Q4-1 : We have designed our customized board based on TMS320C6657 EVM as can be seen attached schematic. Boot Device configuration pin is BOOTMODE[3:0], right?
Q4-2 : What does PLL Multiplier signify? Does that mean CORECLK?
5. About Boot Strap Configuration.
Q5-1: When using EMIF16 NAND Flash for booting, how do I set the Boot Strap Configuration for above schematic.
(Coreclk : 50MHz, DDRCLK : 50MHz, PCIE Unused)
Q5-2 : When using EMIF16 NOR Flash(32MB) for booting, how do I set the Boot Strap Configuration for above schematic?
(Coreclk : 50MHz, DDRCLK : 50MHz, PCIE Unused)
Case 1 : If we are using IBL booting...
Case 2 : if we are not using IBL booting...
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[TDA4M] Questions about PSDK SPI Test on TDA4M EVM Board
Dear Ti members,
I would like to test the SPI communication between the MCU and Main domain using PSDK 0.9 SW on the TDA4M EVM board.
I have some questions about this as below.
1. According to the mcusw release document, SPI communication test between MCU and Main domain A72 is completed through MCUSS Demo App based on RTOS.
Is the psdk 0.9 version of the SPI communication test complete? Error occurs due to header file when building ipc_spi_slave code of MCUSS Demo App.
The problem is caused by an invalid header file which is not for TDA4M. ( in ipc_spi_slave_app.c )
Build error reason ==> #include <ti/csl/soc/am65xx/src/cslr_soc.h>
Modify ==> #include <ti/csl/soc/j721e/src/cslr_soc.h>
As there is no code of am65xx, it is impossible to check the comparison, so I request reconfirmation upon completion of SPI communication test.
2. According to the mcusw release document, SPI communication test between MCU and Main domain A72 is completed through MCUSS Demo App based on RTOS.
However, in PSDK 0.9, we know that the Main domain A72 is only Linux supported. I tried to modify the makefile for ipc_spi_slave_app to test on MCU2_0 or MCU2_1,
but it does not build due to linker script( *.lds ) problem. Later I checked in the 0.9 release document that McSPI only supports MPU1_0 and MCU1_0.
In version 0.9, is ipc_spi_slave_app test completely impossible on MCU2 and MCU3 in the main domain? Is it possible in version 1.0
3. I downloaded the kernel code from PSDK 0.9 Linux version and confirmed that the SPI Slave Driver code ( spi_omap2_mcspi.c ) exists.
1) I need to add and to modify code to use this driver ( the driver is not included now ), so I will be working on it. Can you give me a guide on how to modify and build for using this driver?
( I have no experience with Yocto base. )
2) There are two SPI test examples in the "tools/spi" path. Are there any additional examples? And is it possible to slave test with SPIdev_test.c file?
( I will test by connecting MCU as Master and Main domain as slave. )
Please let me know your opinion.
Thank you.
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TMS320C6678: no symbols are deifned for 0x
Part Number: TMS320C6678
Hi,
The customer has created two tasks in his project. When the project ran in full speed and then be paused, the project stopped and the log file displayed "no symbols are deifned for 0x80362056". The project didn't stop within while(1) and the address is different everytime.
0x80362056 points to .text in DDR3
80361c60 000000a0 sysbios.ae66 : BIOS.obj (.text:ti_sysbios_family_c64p_Hwi_eventMap__E)
80361d00 000000a0 : BIOS.obj (.text:ti_sysbios_family_c64p_Hwi_getStackInfo__E)
80361da0 000000a0 : BIOS.obj (.text:ti_sysbios_heaps_HeapMem_init__I)
80361e40 000000a0 : BIOS.obj (.text:ti_sysbios_knl_Event_pendTimeout__I)
80361ee0 000000a0 : BIOS.obj (.text:ti_sysbios_knl_Idle_run__E)
80361f80 000000a0 : BIOS.obj (.text:ti_sysbios_knl_Semaphore_pendTimeout__I)
80362020 000000a0 : BIOS.obj (.text:ti_sysbios_knl_Task_deleteTerminatedTasksFunc__I)
803620c0 000000a0 : BIOS.obj (.text:ti_sysbios_knl_Task_processVitalTaskFlag__I)
80362160 000000a0 : BIOS.obj (.text:ti_sysbios_timers_timer64_Timer_stop__E)
80362200 000000a0 rts6600_elf.lib : lowlev.obj (.text:write)
803622a0 000000a0 ti.targets.rts6000.ae66 : Assert.oe66 (.text:xdc_runtime_Assert_raise__I)
80362340 000000a0 : LoggerBuf.oe66 (.text:xdc_runtime_LoggerBuf_Module_startup__F)
803623e0 000000a0 helloWorld_pe66.oe66 (.text:xdc_runtime_LoggerBuf_write8__E)
80362480 000000a0 ti.targets.rts6000.ae66 : Text.oe66 (.text:xdc_runtime_Text_xprintf__I)
80362520 00000080 ti.drv.cppi.ae66 : cppi_drv.oe66 (.text:Cppi_setCpdmaLoopback)
803625a0 00000080 stk6_ppp_pppoe.ae66 : md5.oe66 (.text:Decode)
Is it related to project or related to build command?
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Linux/AM6548: UART receive errors
Part Number: AM6548
Tool/software: Linux
Hi
I have some problem when I use uart
The EVM board can not receive data fully,there are some data missing and some data errors.
Reproduce:
1. sdk version:
root@am65xx-evm:~# uname -a
Linux am65xx-evm 4.19.38-g4dae378bbe #14 SMP PREEMPT Mon Aug 5 14:38:57 CST 201x
2.Test steps:
set the uart baud rate: 9600
PC program :uart_send.sh
#!/bin/bash
count=1000;
for((i=1;i<=$count;i++));
do
echo "0;1;3;4;6;7;8;9;a;b;c;d;e;f;10;11;12;13;14;15;16;17;18;19;1a;1b;1c;1d;1e;1f;20;21;22;23;24;25;26;27;28;29;2a;2b;2c;2d;2e;2f;30;31;32;33;34;35;36;37;38;39;3a;3b;3c;3d;3e;3f;40;41;42;43;44;45;46;47;48;49;4a;4b;4c;4d;4e;4f;50;51;52;53;54;55;56;57;58;59;5a;5b;5c;5d;5e;5f;60;61;62;63;64;65;66;67;68;69;6a;6b;6c;6d;6e;6f;70;71;72;73;74;75;76;77;78;79;7a;7b;7c;7d;7e;7f;80;81;82;83;84;85;86;87;88;89;8a;8b;8c;8d;8e;8f;90;91;92;93;94;95;96;97;98;99;9a;#a3" > /dev/ttyUSB3;
done
EVM:uart_recv.sh
#!/bin/bash
while (true);
do
cat /dev/ttyS1 > test.txt;
done
Firstly,execute uart_recv.sh on the evm and then execute uart_send.sh on the pc
Result: (Please visit the site to view this file)
can use "#" to count how many items I have received.
I have send 1000 counts items ,but I have only receive 991 items.
besides there are some items error,maybe there are some space or error data.
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PROCESSOR-SDK-TDAX: [TDA4M] Where is the TIOVX tutorial?
Part Number: PROCESSOR-SDK-TDAX
Hi,
In "pytiovx_guide/index.html#KERNEL_SCRIPT", there is "See also examples in TIOVX tutorial [HTML] for making OpenVX usecases using PyTIOVX too".
But, when I click the "HTML", there is no site.
Where can I find the TIOVX tutorial?
BR,
Heechang
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AMIC110: EDMA3 memory protection
Part Number: AMIC110
Hi,
There is MPPAG and MPPA_m registers for memory protection, specifying user and supervisor levels of read write and execute actions. How to define user and supervisor?
Are they related to the mechanism of processor function or upper level application?
For upper level application, operation user and supervisor could be seperated with assigning different DMA channels without worrying about overlap access.
Kind regards
Orient
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Linux/BEAGLEBK: Saving U-boot environment
Part Number: BEAGLEBK
Tool/software: Linux
How to save uboot.env from userspace like fw_setenv?
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AM5728: Fvid2_start problem
Part Number: AM5728
My project uses VIP on board AM572X EWM. After power on from SD card A15 boots MLO. Then MLO starts C66 which configurates FVID2 drivers. When I start C66 in baremetal FVID2 works. But when I start C66 under RTOS FVID2 stops on the FVID2_start(). The problem is like https://e2e.ti.com/support/processors/f/791/t/783033?RTOS-AM5728-boot-from-sd-card-and-the-app-stopped-at-Fvid2-start-. The update of PDK to the version of 1_0_15 didn't do any results. What is the solution of this problem? Please help me!
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CCS/TMS320C6678: SRIO : Send DIO packets continuously
Part Number: TMS320C6678
Tool/software: Code Composer Studio
Hello,
I want to send and receive Direct I/O packets between DSP (C6678) and xilinx FPGA with 1.25, 2.5, 3.125, and 5 Gbps rates.
Problem 1:
I studied SRIO_Loopback_evmc6678_C66BiosTestProject example project of SRIO.
In this example, 10 iterations of NWRITE_R packets are send via test_dioSockets() function as follow.
/* Send the DIO Information. */
if (Srio_sockSend (srioSocket, srcDataBuffer, SIZE_DIO_PACKET, (Srio_SockAddrInfo*)&to) < 0)
{
System_printf ("Debug(Core %d): DIO Socket Test Failed\n", coreNum);
return -1;
}
/* Loop around till the transfer is complete. */
while (1)
{
/* Get the completion code. */
if (Srio_getSockOpt(srioSocket, Srio_Opt_DIO_SOCK_COMP_CODE, &compCode, sizeof(uint8_t)) < 0)
{
System_printf ("Error: Unable to get the completion code\n");
return -1;
}
/* Was the transfer complete? */
if (compCode != 0xFF)
break;
}
As shown in this code, the next NWRITE_R packet is sent when completion code of previous NWRITE_R packet is equal to 0. It means that sending of the previous NWRITE_R packet was completed.
Also in this situation, I think that when completion code of previous NWRITE_R packet is equal to 0, it means that the response packet related to NWRITE_R was received.
My first question is:
In the above example, since the next NWRITE_R packet waits until completion of previous NWRITE_R packet (receiving response packet related to previous NWRITE_R), it is not possible to send new NWRITE_R packets. Therefore, it is not possible to achieve the maximum throughput. Is there any way to send DIO packets (such as NWRITE_R) continuously to achieve the maximum throughput?
Problem 2:
As I said, I want to send and receive Direct I/O packets between DSP (C6678) and xilinx FPGA with 1.25, 2.5, 3.125, and 5 Gbps rates.
I studied SRIO_TputBenchmarking_evmc6678_C66TestProject example project of SRIO.
Also, I studied Throughput Performance Guide for C66x KeyStone Devices as well as KeyStone Architecture Serial Rapid IO (SRIO) documents.
In KeyStone Architecture Serial Rapid IO (SRIO) document, it was written that:
Also in the example project, the payload size is considered 8 to 8192 bytes.
My second question is:
The maximum payload size is 256 bytes on FPGA side. But on dsp side, it is possible to consider more than 256 bytes (because of packet segmentation).
In this situation, when I send one NWRITE_R packet with 512 bytes payload size from dsp side, I will receive two different NWRITE_R packets with 256 bytes payload size on FPGA? And I should make and send two separate NWRITE_R response packets from FPGA side to dsp side?
Best Regards,
Mohammad
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TMS320C6655: PCIe issue with windows 10 of Host
Part Number: TMS320C6655
Dear Champs,
Could you please let me know if you have noticed any issues with latest windows10 PC?
My customer found an issue to work with latest windows 10 version although there was no issue with previous one as below.
e.g. in latest windows 10 LTSC(version1803), my customer found PCIe was not recognized at initial boot time, but after that, PCIe was recognized after reboot.
windows PCIe driver was made by my customer, and want to know if there are anyone who have any similar issue with latest windows10.
My customer's C6655 board was connected to PC with windows 10 through PCIe.
in previous version of windodws 10, there was no issue.
1. windows 10 Enterprise 2016 LTSB(version 1607).
==> no issue.
2. windows 10 Enterprise LTSC(version 1803).
==> can not recoginze PCIe at initial boot time. but, PCIe was recognized after reboot.
Thanks and Best Regards,
SI.
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AM3354: PMIC_POWER_EN is not asserted on power-up
Part Number: AM3354
Hi,
My customer reported AM3354 power-up failure when the device is power-off then power-up again.
PMIC_POWER_EN signal from AM3354 is not asserted when the issue happens.
Please see attached excel for details.
(Please visit the site to view this file)
I found similar issue reported below E2E, but it was not clear if the issue was understood and solved.
It discussed VRTC and RTC_PORZ timing.
https://e2e.ti.com/support/processors/f/791/t/768660
As you can see the sheet#3 in the attachment, RTC_PORZ is driven to high as soon as VRTC is on in customer’s system.
Does it cause an issue?
Thanks and regards,
Koichiro Tashiro
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TDA2SG: About YUV422 Progressive BT.601 Displayout
Part Number: TDA2SG
Dear Sir,
We use Process vision sdk version - 02.10.00.
We plan to use YUV422 Progressive BT.601 Displayout for compitiable.
According to http://processors.wiki.ti.com/index.php/PDK/PDK_Application_Notes_Video_Driver_Porting#DSS_Configuration,
only RGB mode output for BT.601
How can I config YUV422 Progressive BT.601 format in Display?
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TMS320C6678: To update the descriptor value
Part Number: TMS320C6678
Hi,
I am working on qmss project . As of now I have completed the moving of descriptor to the free queue, popping it by giving an handle, later pushing it to an other newly defined queue.
I want the value of the descriptor to be changed before I push it to the new queue. How do we do that?? where do we get the direct access to descriptor??
Please help me with a part of code.
Thanks and regards.
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DRA718: Couldn't load WS module libpvrws_WAYLAND.so
Part Number: DRA718
Hi,
Customer gets the following log:
- failed to load module: /usr/lib/gbm/gbm_dri.so: cannot open shared object file: No such file or directory
- failed to load module: /usr/lib/gbm/gbm_gallium_drm.so: cannot open shared object file: No such file or directory
- PVR:(Error): Couldn't load WS module libpvrws_WAYLAND.so [0, ]
Can you please help find the location where these logs are printed out? The 3rd log costs about 30 milliseconds, which customer wants to optimize and bypass check wayland.
Thanks.
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AM5728: SPI read issue
Part Number: AM5728
Hi,
I am using the three different spi devices on a single bus.
what i observed is when i connect the three devices, am getting corrupted data on the one device when i read the data on selected device.
Even though i have not programmed other devices. when i remove other devices clock data read happens without corruption.
can anyone have gone through this type of issue.Please suggest me on this.
I have checked with the pinmux also its fine.
bios version: 6_52_00_12
pdk ver: pdk_am57xx_1_0_7
thanks
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