Part Number: AM6548
Hi Experts,
Could you let me know the TeraNet bandwidth for AM65xx?
For example, 66AK2E05 has these spec I believe.
Part Number: AM5728
Tool/software: TI-RTOS
Hi，
I want to build the VISION SDK on AM5728.I know the default compile options are TDA2x, TDA3x, TDA2Ex, TDA2Px.
There is no am572x configuration in the compile options.Do you have any way?
How to build VISION SDK on AM57xx series?
Best regards，
Able
Part Number: AM4372
Our client is trying RAMFS boot with BSP of AM4372 referring to "Processor SDK Linux Software Developer's Guide".
They seem to follow the document like the following log, but it seems to be running from SD / MMC.
$ mkdir target_fs $ cd target_fs $ tar xf ../filesystem/arago-tiny-image-am437x-evm.tar.xz $ find . | cpio -H newc -o > ../target_fs.cpio 26631 blocks $ cd .. $ gzip target_fs.cpio U-Boot# setenv boot ramfs U-Boot# setenv server_ip 192.168.200.3 U-Boot# setenv ipaddr 192.168.200.14 U-Boot# setenv tftp_root target_fs.cpio.gz U-Boot# setenv name_fs target_fs.cpio.gz U-Boot# saveenv Saving Environment to FAT... writing uboot.env done U-Boot# boot switch to partitions #0, OK mmc0 is current device SD/MMC found on device 0 reading uEnv.txt 717 bytes read in 5 ms (139.6 KiB/s) Loaded environment from uEnv.txt Importing environment from mmc ... 4355472 bytes read in 243 ms (17.1 MiB/s) 42675 bytes read in 51 ms (816.4 KiB/s) Booting from mmc0 ... Kernel image @ 0x82000000 [ 0x000000 - 0x427590 ] ## Flattened Device Tree blob at 88000000 Booting using the fdt blob at 0x88000000 Loading Device Tree to 8fff2000, end 8ffff6b2 ... OK Starting kernel ... ： ： root@am437x-evm:~# df Filesystem 1K-blocks Used Available Use% Mounted on /dev/root 2306316 748556 1437276 34% / devtmpfs 501936 4 501932 0% /dev tmpfs 514356 220 514136 0% /run tmpfs 51200 284 50916 1% /var/volatile /dev/mmcblk0p1 71133 569 70565 1% /run/media/mmcblk0p1 /dev/mmcblk0p3 4810396 1781388 2777996 39% /run/media/mmcblk0p3
Is there anything wrong? Or is there a place we should check?
Part Number: AM3352
Hi,
I am getting the following error, while booting linux,
omap_voltage_late_init: Voltage driver support not added
I have been going through the documentation provided in linux, which is relevant to this current problem.
I have observed that this has something to deal with the voltage and frequency maps which should be present in the DT, is that right ?
Also, I have seen that under arch/arm/mach-omap2/ there are three files mainly dealing with this,
io.c ->
#ifdef CONFIG_SOC_AM33XX
void __init am33xx_init_early(void)
{
omap2_set_globals_tap(AM335X_CLASS,
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
omap2_control_base_init();
omap3xxx_check_revision();
am33xx_check_features();
omap2_prcm_base_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
am33xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = am33xx_dt_clk_init;
}
void __init am33xx_init_late(void)
{
omap_common_late_init();
}
#endif
pm.c ->
int __init omap2_common_pm_late_init(void)
{
/* Init the voltage layer */
omap3_twl_init();
omap4_twl_init();
omap_voltage_late_init();
/* Initialize the voltages */
omap3_init_voltages();
omap4_init_voltages();
/* Smartreflex device init */
omap_devinit_smartreflex();
return 0;
}
voltage.c ->
int __init omap_voltage_late_init(void)
{
struct voltagedomain *voltdm;
if (list_empty(&voltdm_list)) {
pr_err("%s: Voltage driver support not added\n",
__func__);
return -EINVAL;
}
list_for_each_entry(voltdm, &voltdm_list, node) {
struct clk *sys_ck;
if (!voltdm->scalable)
continue;
sys_ck = clk_get(NULL, voltdm->sys_clk.name);
if (IS_ERR(sys_ck)) {
pr_warn("%s: Could not get sys clk.\n", __func__);
return -EINVAL;
}
voltdm->sys_clk.rate = clk_get_rate(sys_ck);
WARN_ON(!voltdm->sys_clk.rate);
clk_put(sys_ck);
if (voltdm->vc) {
voltdm->scale = omap_vc_bypass_scale;
omap_vc_init_channel(voltdm);
}
if (voltdm->vp) {
voltdm->scale = omap_vp_forceupdate_scale;
omap_vp_init(voltdm);
}
}
return 0;
}FYI,
I am using a custom board based on AM3352.
DTS includes,
#include "am33xx.dtsi"
DTS has the following entry for cpu,
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
};
};
Part Number: AM3359
Hi,
Please reply as soon as possible as it is urgent.
This is my first time working with linux and AM3359 ICE. I am trying to implement the UARTecho example given in am335x_sysbios_ind_sdk_prebuilt_01_00_00_08. For flashing the SD card i am using APP and MLO files. But i am not getting anything on terminal. I think, i am doing something wrong or missing the steps. So please can anybody tell what are the steps/procedure to implement UARTecho example??
Regards,
Digvijay
Hi,
Only Linux is supported at CA72 in the latest sdk v0.9 of TDA4.
But in your previous TDA2, RTOS version was the main platform at CA15.
When will RTOS be supported at CA72?
Regards,
HJ Kim
Part Number: PROCESSOR-SDK-AM335X
Hi,
I am working on am335x based board. Altera max 10 fpga chip is connected via gpmc interface. This fpga chip is supposed to be used as a dp ram.
For time being sof firmware file is flashed to fpga via jtag after linux boots up.
I want to test and verify that fpga is up and working fine by reading/writing some values to it.
I think I can use devmem2 tool for this purpose. But
1) I don't know how to derive start and end address of fpga. In TRM, GPMC addresses are given as 0x0000_0000 to 0x1FFF_FFFF. Is this the address range I should use in my code?
2) Also I am not sure whether this fpga is detected by kernel and correct drivers are being used or not
Here I have given every possible detail, please ask if more info is needed.
1) tisdk_am335x-evm_defconfig
CONFIG_ARCH_SOCFPGA=y CONFIG_ALTERA_STAPL=y CONFIG_FPGA=y CONFIG_FPGA_MGR_SOCFPGA=y
free command shows total mem = 1026524 before enabling these flags
free command shows total mem = 1028852 after enabling these flags. So driver has detected some extra ram?
2) am335x-evm.dts
gpmc_pins_default: gpmc_pins_default {
pinctrl-single,pins = <
/******************** FPGA Through GPMC Interface **********************/
/* Control Lines */
0x8C (PIN_OUTPUT | MUX_MODE0) /* GPMC_CLK */
0x98 (PIN_OUTPUT | MUX_MODE0) /* GPMC_nWE */
0x94 (PIN_OUTPUT | MUX_MODE0) /* GPMC_OEn_REn.GPMC_nRE */
0x7C (PIN_OUTPUT_PULLUP | MUX_MODE0) /* GPMC_nCS0.GPMC_DPRAM_nCS0 */
/* Address Lines */
0xA0 (PIN_OUTPUT | MUX_MODE1) /* LCD_DATA[0].gpmc_a0 */
0xA4 (PIN_OUTPUT | MUX_MODE1) /* LCD_DATA[1].gpmc_a1 */
0xA8 (PIN_OUTPUT | MUX_MODE1) /* LCD_DATA[2].gpmc_a2 */
0xAC (PIN_OUTPUT | MUX_MODE1) /* LCD_DATA[3].gpmc_a3 */
0xB0 (PIN_OUTPUT | MUX_MODE1) /* LCD_DATA[4].gpmc_a4 */
0xB4 (PIN_OUTPUT | MUX_MODE1) /* LCD_DATA[5].gpmc_a5 */
0xB8 (PIN_OUTPUT | MUX_MODE1) /* LCD_DATA[6].gpmc_a6 */
0xBC (PIN_OUTPUT | MUX_MODE1) /* LCD_DATA[7].gpmc_a7 */
0xE0 (PIN_OUTPUT | MUX_MODE1) /* LCD_VSYNC.gpmc_a8 */
0xE4 (PIN_OUTPUT | MUX_MODE1) /* LCD_HSYNC.gpmc_a9 */
/* Data Lines */
0x00 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_d0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_d1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_d2 */
0x0C (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_d3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_d4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_d5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_d6 */
0x1C (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_d7 */
0xEC (PIN_OUTPUT | MUX_MODE7) /* LCD_AC_BIAS_EN.gpio2[25] FPGA_SOFT_RST */
0x21C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* USB_DRVVBUS.gpio0[18] nFPGA_STATUS */
/* 0x18C (PIN_INPUT_PULLDOWN | MUX_MODE7) */ /* UART2_RTSn.gpio3[6] FPGA_CRC_ERR */
0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* UART2_RXD.gpio0[2] FPGA_PRIMARY_PWR */
0x15C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* SPI0_CS0.gpio0[5] FPGA_PWR_BACKUP */
0x1B0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* SPI1_CS1.gpio0[19] FPGA_CFG_DONE */
0x234 (PIN_OUTPUT | MUX_MODE7) /* USB1_DRVVBUS.gpio3[13] FPGA_nCFG */
0x88 (PIN_OUTPUT | MUX_MODE7) /* GPMC_CSn3.gpio2[0] FPGA_SOM_RST */
/* 0x188 (PIN_OUTPUT | MUX_MODE7) */ /* I2C0_SDA.gpio3[5] FPGA_DEV_OE */
0x160 (PIN_OUTPUT | MUX_MODE7) /* SPI0_CS1.gpio0[6] FPGA_CFG_SEL */
>;
/******************** FPGA Through GPMC Interface **********************/
};&gpmc {
pinctrl-names = "default";
pinctrl-0 = <&gpmc_pins_default>;
status = "okay";
};3) am33xx.dtsi
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
ti,no-idle-on-init;
reg = <0x50000000 0x2000>;
interrupts = <100>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};4)
-sh-3.2# cat /proc/iomem | grep gpmc
50000000-50001fff : /ocp/gpmc@50000000
5)
-sh-3.2# devmem2 0x00000fff
/dev/mem opened.
Memory mapped at address 0xb6fa2000.
Bus error (core dumped)
-sh-3.2# devmem2 0x50000000
/dev/mem opened.
Memory mapped at address 0xb6fa9000.
Read at address 0x50000000 (0xb6fa9000): 0x00000060
6)
-sh-3.2# dmesg | grep gpmc
[ 0.240149] omap-gpmc 50000000.gpmc: could not find pctldev for node /ocp/l4_wkup@44c00000/scm@210000/pinmux@800/gpmc_pins_default, deferring probe
[ 1.442795] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[ 1.448148] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[ 1.454482] gpiochip_add: registered GPIOs 510 to 511 on device: omap-gpmc
Part Number: AM3358
Hi,
The customer migrated uboot2019 to his board successfully. He has removed eeprom and initialized sdram. But Saveenv failed as below.
Part Number: AM5728
Hello,
I am trying to run a capture-based application which uses libdce but it seems to be missing from the PSDK 5_03 filesystem.
The link provided in the software manifest (git://git.omapzoom.org/repo/libdce.git;protocol=git) also doesn't seem to work.
Can anyone suggest a way to incorporate this library into PSDK 5?
Regards,
Nikhil
Part Number: 66AK2H14
Tool/software: TI-RTOS
Hello sir/madam,
My project I regarding the qmss data transfer execution, I am not able to analyze the concept and get the hardware implementation on k2l board. Please help me with this
Thankyou
Regards.
Part Number: AM6548
Tool/software: Linux
Dear Ti
when the SDK6.0 release, uart has enable the uart DMA function.
I have done the test on the EVM board,But when send huge data to the board,the board can not receive correctly.
the error info:
root@am65xx-evm:~# [ 6488.741391] rcu: INFO: rcu_preempt self-detected stall on CPU
[ 6488.747153] rcu: 0-....: (5250 ticks this GP) idle=8da/1/0x4000000000000004 softirq=30313/30313 fqs=2278
[ 6488.749384] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[ 6488.756787] rcu: (t=5253 jiffies g=59941 q=1447)
[ 6488.767481] Task dump for CPU 0:
[ 6488.767490] rcu: 0-....: (5264 ticks this GP) idle=8da/1/0x4000000000000004 softirq=30300/30313 fqs=2298
[ 6488.767495] rcu:
[ 6488.770715] uart_loopback R
[ 6488.780346] (detected by 2, t=5259 jiffies, g=3713, q=1)
[ 6488.782347] running task
[ 6488.785306] Task dump for CPU 0:
[ 6488.790604] 0 1297 1038 0x00000002
[ 6488.793646] uart_loopback R
[ 6488.796863] Call trace:
[ 6488.800858] running task
[ 6488.803832] dump_backtrace+0x0/0x158
[ 6488.806255] 0 1297 1038 0x00000002
[ 6488.809302] show_stack+0x14/0x20
[ 6488.812948] Call trace:
[ 6488.816952] sched_show_task+0x13c/0x168
[ 6488.820262] __switch_to+0x94/0xd0
[ 6488.822692] dump_cpu_task+0x40/0x50
[ 6488.826605] lock_timer_base+0x60/0xc0
[ 6488.829996] rcu_dump_cpu_stacks+0x90/0xcc
[ 6488.833556] try_to_del_timer_sync+0x2c/0x88
[ 6488.837294] rcu_check_callbacks+0x6c8/0x850
[ 6488.841377] del_timer_sync+0x44/0x58
[ 6488.845637] update_process_times+0x2c/0x70
[ 6488.849895] schedule_timeout+0x1a0/0x338
[ 6488.853546] tick_sched_handle.isra.5+0x3c/0x48
[ 6488.857713] wait_for_common+0x140/0x168
[ 6488.861711] tick_sched_timer+0x48/0x98
[ 6488.866225] (null)
[ 6488.870138] __hrtimer_run_queues+0x118/0x1a8
[ 6488.881261] hrtimer_interrupt+0xe4/0x240
[ 6488.885264] arch_timer_handler_phys+0x2c/0x38
[ 6488.889701] handle_percpu_devid_irq+0x80/0x138
[ 6488.894222] generic_handle_irq+0x24/0x38
[ 6488.898222] __handle_domain_irq+0x60/0xb8
[ 6488.902308] gic_handle_irq+0x7c/0x178
[ 6488.906048] el1_irq+0xb0/0x128
[ 6488.909181] __do_softirq+0x94/0x208
[ 6488.912750] irq_exit+0xb8/0xc8
[ 6488.915883] __handle_domain_irq+0x64/0xb8
[ 6488.919969] gic_handle_irq+0x7c/0x178
[ 6488.923709] el1_irq+0xb0/0x128
[ 6488.926846] mem_serial_out+0xc/0x20
[ 6488.930415] serial8250_startup+0x14/0x28
[ 6488.934417] uart_startup.part.9+0x150/0x258
[ 6488.938677] uart_port_activate+0x4c/0x60
[ 6488.942680] tty_port_open+0x84/0xd8
[ 6488.946247] uart_open+0x34/0x48
[ 6488.949468] tty_open+0xfc/0x3e0
[ 6488.952691] chrdev_open+0xa4/0x1a0
[ 6488.956174] do_dentry_open+0x110/0x340
[ 6488.960003] vfs_open+0x28/0x30
[ 6488.963138] path_openat+0x268/0x1000
[ 6488.966792] do_filp_open+0x78/0xf0
[ 6488.970274] do_sys_open+0x170/0x210
[ 6488.973841] __arm64_sys_openat+0x20/0x28
[ 6488.977843] el0_svc_common+0x84/0xf0
[ 6488.981497] el0_svc_handler+0x2c/0x80
[ 6488.985237] el0_svc+0x8/0xc
Part Number: TDA2SX
We known multi-channel cameras based on TDA2P MIPI interface via TI official website: TDA2P + DS90UB960 or DS90UB953;
but we are familiar with TDA2S platform, we developed 720p(1280*720) surrounded view cameras and ADAS function.
We want to evaluate possibility of TDA2S + 1080p(1920*1080) surrounded view cameras + ADAS:
1. Surrounded view cameras: 4pcs 1080 camera raw data;
2. Please recommend serializer and deserializer:
Part Number: AM3358
Hi,
The above table in TRM shows, if i used mmc 1-bit mode, DAT[1]~DAT[7] are in Hi-Z mode. Is that mean i cannot use DAT[1]~DAT[7] as GPIO or other function? And there are two group of mmc data pins, Is that mean i can use the other group pins?
Part Number: AM3357
Tool/software: Code Composer Studio
Hi,
We have been working with the AM335x as an ethercat slave and with Twincat as master without any problem, but one of our customer wants to work with Soem https://github.com/OpenEtherCATsociety/SOEM or Etherlab Master https://etherlab.org/en/ethercat/,
Part Number: TMS320VC5509A
Hi,
I received a Modular EVM Motherboard(MMB0 REV D) module for some DAC application. After installing all the required drivers, I was able to access the MMBO module and DAC board somehow.
But from couple of days, when I connect the USB to the board , the USB is not getting enumerated and device is not shown in the device manager.
After debugging the board, observed that the voltage level on DP line of USB was low though there was a pull up resistor connected from PU pin of the DSP tms320vc5509apge and DP line. When I refered the datasheet of tms320vc5509apge, it was given that PU pin will be connected to USBVDD supply internally through a software controllable switch CONN bi tog USBCTL register, but I am not sure of the value present in that particular bit also I don't have any other interface to program the registers in DSP. Just to check if the USB works good with pull up, I connected external pull up on the PUR that is connected on DP line, then USB device enumerated but was shown as unknown device by PC as the device was not able to send K chirp data.
Can someone please help me in finding what may be the reason why I am not getting pull up on DP line from the DSP ?, or someone please suggest some way to program DSP in the MMB0 board other than using USB.
Thanks,
MADHU.
Part Number: AM5708
RTOS SDK:ti-processor-sdk-rtos-am57xx-evm-06.00.00.07
CPU:AM5708
RAM:512M
My board boot time is 90 seconds and I feel an abnormal boot time.
How long is the normal startup time of AM5708 RTOS evaluation board?
Part Number: TMS320C6678
Tool/software: TI C/C++ Compiler
Hi,
I have the little test code below which I load onto all cores. It parallelizes some matrix multiplication. Stuff works fine without -o3. If I define -o3, then stuff works fine if I'm not doing the matrix multiplication (#udef MATMPY below). But as soon as I define -o3 and MATMPY some cores will be hung just before returning from main.
Any idea what I should look into? Because the cores are hung I actually can not see at which function/symbol they are hanging.
Note that the IPC framework mentioned in the code simply consists of some flags in an uncacheable shared memory location (done in config_cache with MPAX). Also note that in order to exclude any conflicts I disabled all BIOS components and switched from System_printf to printf. Finally, note that due to the print statement at the end I am quite sure that they hang just before return.
Thanks a million for your help.
Best wishes,
Idris
main.c:
#pragma DATA_SECTION(out_vec, ".shared_section")
#pragma DATA_ALIGN(out_vec, 2)
volatile float out_vec[NROWS * 2 * NUMSLAVES];
#pragma DATA_SECTION(in_vec, ".shared_section")
#pragma DATA_ALIGN(in_vec, 2)
volatile float in_vec[NCOLS * 2 * NUMSLAVES];
#pragma DATA_SECTION(in_mat, ".shared_section")
#pragma DATA_ALIGN(in_mat, 2)
volatile float in_mat[NCOLS * NROWS * 2 * NUMSLAVES];
#pragma DATA_SECTION(selfId, ".local_data")
volatile Uint32 selfId;
int main(void) {
CACHE_invAllL1d(CACHE_WAIT);
_mfence();
const int NUM_ROUNDS = 10;
selfId = CSL_chipReadReg(CSL_CHIP_DNUM);
int round_i;
config_cache(selfId);
/* Initialise variables and sync */
if (selfId == 0) { // MASTER
ipc_master_init();
ipc_master_wait_for_slaves_after_init();
/* Initialize matrices and vectors */
init_cplx_vec(in_vec, NCOLS * NUMSLAVES, 1.0);
init_cplx_vec(out_vec, NCOLS * NUMSLAVES, 3.5);
int block_i;
for (block_i = 0; block_i < NUMSLAVES; block_i++)
init_cplx_vec(&in_mat[block_i * NROWS * NCOLS * 2],
NCOLS * NROWS, (float)(block_i + 1));
CACHE_wbInvAllL1d(CACHE_WAIT);
_mfence();
/* Synchronise all slaves */
ipc_master_set_req(1);
ipc_master_wait_ack();
} else { // SLAVE
/* Initialize IPC framework */
ipc_slave_init2();
/* Sync call */
ipc_slave_wait_req();
ipc_slave_set_ack(1);
}
/***************************************************************
**************************** MASTER ***************************
***************************************************************/
if (selfId == 0) { // MASTER
/* Wait a bit */
simpleDelay();
#if TIMINGLEVEL >= 1
init_timer();
int t0, t1;
t0 = _itoll(TSCH, TSCL);
#endif
for (round_i = 0; round_i < NUM_ROUNDS; round_i++) {
#if TIMINGLEVEL >= 1
t0 = _itoll(TSCH, TSCL);
#endif
/***********************
* REQUEST from slaves *
***********************/
ipc_master_set_req(1);
/****************************
* Wait for ACKNOWLEDGEMENT *
****************************/
ipc_master_wait_ack();
#if TIMINGLEVEL >= 1
t1 = _itoll(TSCH, TSCL);
printf("round_%d: %d cycles (NUMSLAVES=%d)\n", round_i, (t1-t0), NUMSLAVES);
#endif
}
/***************************************************************
**************************** SLAVES ***************************
***************************************************************/
} else { // SLAVE
ipc_slave_reset_num_requests();
do {
/********************
* Wait for REQUEST *
********************/
ipc_slave_wait_req();
#ifdef MATMPY
matvecmpy(&in_mat[(selfId - 1) * NROWS * NCOLS * 2],
&in_vec[(selfId - 1) * NCOLS * 2],
&out_vec[(selfId - 1) * NROWS * 2],
NROWS, NCOLS);
//CACHE_wbInvAllL1d(CACHE_WAIT);
//CACHE_wbL1d ((void *) &out_vec[(selfId - 1) * NROWS * 2], NROWS * 2 * sizeof(float), CACHE_WAIT);
#endif
/***********************
* ACKNOWLEDGE request *
***********************/
ipc_slave_set_ack(1);
} while (ipc_slave_get_num_requests() < NUM_ROUNDS);
}
if (selfId == 0) { // MASTER
int slave_i;
/* Call slaves one by one before terminating */
int i;
for (i = 1; i <= NUMSLAVES; i++) {
#if DEBUGLEVEL >= 0
printf("Calling slave %d\n", i);
#endif
ipc_master_set_req_slave_i(1, i);
ipc_master_wait_ack_slave_i(i);
}
CACHE_wbInvAllL1d(CACHE_WAIT);
_mfence();
} else {
/* Wait until being called */
ipc_slave_wait_req();
#if DEBUGLEVEL >= 0
printf("slave %d reached the end!\n", selfId);
#endif
CACHE_wbInvAllL1d(CACHE_WAIT);
_mfence();
ipc_slave_set_ack(1);
}
return 0;
}
config_cache:
void config_cache(Uint32 selfId) {
/* All cores map MSMCSRAM_NC_VIRT to MSMCSRAM_NC_PHY */
__TI_setMPAX(3, MSMCSRAM_NC_START_ADDR, MSMCSRAM_START_ADDR, 0x10);
/* Disable cache for MSMCSRAM_NC_VIRT (MAR160 & 161) */
Uint8 MAR_NOCACHE = 160;
CACHE_disableCaching(MAR_NOCACHE);
MAR_NOCACHE = 161;
CACHE_disableCaching(MAR_NOCACHE);
/* Enable cache for DDR3 */
const Uint8 MAR_CACHE_START = 128;
const Uint8 MAR_CACHE_END = 135;
int i;
for (i = MAR_CACHE_START; i <= MAR_CACHE_END; i++)
CACHE_enableCaching(i);
/* Invalidate all caches */
CACHE_invAllL1dWait();
CACHE_invAllL2Wait();
/* Wait until all memory operations terminate */
_mfence();
}
Part Number: PROCESSOR-SDK-OMAPL138
Tool/software: TI-RTOS
Hello,
I'm using the latest SDK and I have a problem with FTP data transfer.
I changed the size of the send/receive buffer by using:
setsockopt(ioh->data_socket, SOL_SOCKET, SO_SNDBUF, &valSnd, sizeof(valSnd));
setsockopt(ioh->data_socket, SOL_SOCKET, SO_RCVBUF, &val, sizeof(val));
When I used default size of the the send/receiver buffer my data transfer suspended!
When I changed the size to 2048, transfer of ONE file is fine, but when I am trying send/receive more then one file my transfer suspended.
The next observation: when I changed buffer size to 1kB data transfer is OK (also for parallel transfer of more than one file), but speed transfer is very very slow!
I noticed that when my program doesn't receive the ACK form the PC it sends the frame again and in CCS CONSOLE I see (00691.900 TcpTimeoutRexmt: Retransmit Timeout), when I have a small buffer, I see the frames being sent again in Wireshark, but when I have a larger buffer I see only a retransmission frames in the CCS Console (I don't see it in Wireshark) and the transfer suspend here.
What can I do to improve my transfer?
I attach an attachment *.cfg(Please visit the site to view this file)
Part Number: AM3357
Hello,
I'm trying to port PRU-ICSS-EthernetIP_Adapter_01.00.03.04 example to own board based on Sitara AM3357.
Example works OK on ICEV2 and own board when Clock.tickPeriod is set to 500.
Problem begins when I've change Clock.tickPeriod to 1000 (what is desired tickPeriod value).
Interesting is that when I've change Clock.tickPeriod to 499 or 400 then all is ok. When I've change to 501 it's stop working.
Global.ndkTickPeriod = 100;
In bad case program don't reach next line after:
if(EIP_Init(pstEipInit) == EIP_FALSE) in static int EIPAPP_initSample(ST_EIP_INIT *pstEipInit, ST_EIP_ONLINE *pstEipOnline) in EIP_main.c.
When I've pause program than Stack looks like that:
And it's assert on:
BIOS_ThreadType type = BIOS_getThreadType();
Assert_isTrue((type == BIOS_ThreadType_Task),
Semaphore_A_badContext);
What could cause the problem? Is necessary to recompile libethernetip_adapter_stack_AM335x_arm.a?
Best Regards
Paweł Wójcicki
Part Number: PROCESSOR-SDK-OMAPL138
HI ,
I recently added a resource table and config.bld file to my project in order to enable the IPC ( referring the IPC example project avalable in pdk_1_0_6 ). However after the changes I observed that my IRAM/L2 Memory length had reduced from 40000 (256 KB) to 38000 (224 KB ). I would like to know what can be the reasons that might cause a reduction in the IRAM size. Starting address remained the same 0x11800000
thanks
Regards
Deepak