Part Number:AM6548

Hi,

We are using AM6548 SoC in our design. We have used Datasheet Rev F for our board design.

However, it has come to our notice that the revision has been updated to Rev H in June 2019.

There are few changes in the updated datasheet wrt to the old revision datasheets

Listed below are the few changes wrt to previous and updated datasheet versions:

1.The voltage supply that powers the terminal IO buffers for SDCD and SDWP were VDDSHV6. However, in the updated datasheet it is VDDS_OSC1.

2. Unused Balls Specific Connection Requirements

We have SDWP lines pulled up to VDDSHV6.

We are aware that the current chip silicon revision is a pre-production release. We wanted to understand if these changes will be reflected only in the next silicon revision or will be affected in the present build too.  

Kindly advice.

Part Number:AM5718

Tool/software: Linux

I have tested the demo with ep mode,and it works fine.

As I know,the pcie ep can support 8 function on each device,so I want to test another function,such as a hdmi output.It means that the pcie rc send the data to ep side with hdmi display.

How to change the code ?

Thanks

JasonSun

Part Number:AM3352

Tool/software: Linux

Hi

I understand that TPS65217x will get the expected AM3352 core voltage through I2C during boot stage, the AM3352 uboot code communicate with TPS65217x to make PMIC adjust core voltage. My question is:

In boot stage, besides UBOOT code will operate I2C, do SPL and BOOT ROM also communicate with TPS65217x through I2C?

Is there any doc/link to describe the info on uboot communicate with TPS65217x in uboot stage?

Thanks

Part Number:66AK2G12

Tool/software: TI-RTOS

Dear Champs,

There are still hang issue when input audio stream changed and my customer found an issue in the AHCLKR when hang was occurred.

HDMI MCLK was connected to AHCLKR of McASP0 in customer's board, and found below unstable clock while audio stream was changed.

Their SW is PRSDK v5.01 and they used PA framework DEMO in the PRSDK.

Could you please check if below unstable clock in AHCLKR will cause hang in K2G?

If so, could you please let me know how this hang can be avoided?

in below image, K2G will be hang in the interval between arrows.

Thanks and Best Regards,

SI.

Part Number:AM5728

Tool/software: Linux

Hi

Is there any document or web link to describe bootROM-SPL-UBOOT work flow on AM57x?

I would like to understand more details on DDR configuration on SPL, but I can not find any doc on this topic

Thanks.

Part Number:AM6546

Tool/software: Linux

Hi Team,

Our project is using AM6546 IDK , and 2 different IEP (Profinet and Ethernet/IP), These should run in parallel.

As of my understanding is, for each IEP TI will provide PRU Firmware for controlling it. Like wise both Profinet and Ethernet/IP has PRU FW.

For understanding the implementation of FW, Is it available for download ?

This is because, if I have to modify it and to use only one PRU core for IEP control, I may required to multiplex these thing. I can acquire clear idea how it has been implemented.

Thanks and Regards,

Vishnu

Part Number:PROCESSOR-SDK-AM335X

Tool/software: Linux

Hi,

Using Linux Processor SDK version 5.03

I believe that that remoteproc and rpmsg kernel modules are enabled by default from SDK v02.00.02.11 onward and that there is demo firmware loaded to serve as an out of box demo.
I get the following error when I try to run the same. Am I doing something wrong?

root@am335x-evm:~# echo 'am335x-pru0-fw' > /sys/class/remoteproc/remoteproc1/firmware
root@am335x-evm:~# echo 'start' > /sys/class/remoteproc/remoteproc1/state       
[ 5194.448475] remoteproc remoteproc1: powering up 4a334000.pru
[ 5194.454738] remoteproc remoteproc1: Direct firmware load for am335x-pru0-fw f
ailed with error -2
[ 5194.468127] remoteproc remoteproc1: request_firmware failed: -2
[ 5194.478859] remoteproc remoteproc1: Boot failed: -2
-sh: echo: write error: No such file or directory

Part Number:AM5716

Hi,

There is SYS_TICK_TIMER_IRQ(System Tick Timer) in Table 17-4, 5 of AM571x AM570x Technical Reference Manual(spruhz7h.pdf).

Could you tell me which timer is connected with it? Is it TIMER1, TIMER2 or TIMER10?

Best Regards,

Masa.O

Part Number:DRA745

Tool/software: TI-RTOS

Jumping to MPU CPU0 App

TDA2xx SBL Boot

DPLL Configuration Completed

Clock Domain Configuration Completed

Module Enable Configuration Completed

TI EVM PAD Config Completed

DDR Config Completed

App Image Download Begins

SD Boot - file open completed successfully

MPU CPU0 Image Load Completed

IPU1 CPU1 Image Load Completed

IPU2 CPU0 and CPU1 Image Load Completed

DSP1 Image Load Completed

DSP2 Image Load Completed

EVE1 Image Load Completed

EVE2 Image Load Completed

EVE3 Image Load Completed

EVE4 Image Load Completed

App Image Download Completed

Putting MPU CPU1 in Off mode

EVE MMU configuration completed

EVE MMU configuration completed

EVE MMU configuration completed

EVE MMU configuration completed

*****************************************************************

PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles

SBL Initial Config Cycles - 144553 (12.33 ms)
SOC Init Cycles - 164782 (14.6 ms)
DDR Config Clock Cycles - 43438 (3.70 ms)
App Image Load Cycles - 231177367 (19727.13 ms)
Slave Core Bootup Cycles - 208367 (17.78 ms)
SBL Boot-up Cycles - 231739570 (19775.10 ms)
Time at which SBL started IPU1_0 - 7072608 (603.52 ms)
*****************************************************************

Jumping to MPU CPU0 App

It stop here. could you give some comments ? thanks.

Part Number:AM5716

Hi, 

ARM document says Cortex-M4 has Vector Table Offset Register(VTOR).

But I didn't find the description of VTOR in datasheet and TRM.

Could you please tell me which document describe about VTOR?

Especially, I would like to know the address of VTOR.

Best Regards,

Masa.O

Part Number:AM5716

Hi,

MPU connects EMIF directly (not via L3_MAIN interconnect) in "Figure 2-1. Interconnect Overview" of TRM(spruhz7h.pdf).

1) Could you please tell me why direct path exists between MPU and EMIF? Does it mean to prevent bus contention in L3_MAIN interconnect?

2) Could you please tell me which address MPU accesses if MPU accesses EMIF directly? 

    Should I use Q10(0x02 8000 0000-0x02 BFFF FFFF) and Q11(0x02 C000 0000-0x02 FFFF FFFF) instead of Q2(0x8000 0000-0xBFFF FFFF) and Q3(0xC000 0000-0xFFFF FFFF) in Table 2-8? 

3) There is described 3 EMIF1_SDRAM_CS0 area (Q8: 0x02 0000 0000-0x023FFF FFFF,  Q10: 0x02 8000 0000-0x02 BFFF FFFF, Q11: 0x02 C000 0000-0x02 FFFF FFFF) in Table 2-8. Could you please tell me the difference between Q8 and Q10/11?

Best Regards,

Masa.O

Part Number:TDA2PXEVM

Tool/software: Linux

Hello:

   Following is my usecase configuration:

1. If run the usecase disp_dist_src_display separately than the display is ok.
2. If run my usecase without "DispDistSrc_weston -> Display_m4" than thing is ok

Now, if we run both together, the use case will hung on, please see the log (Please visit the site to view this file)

and tried many times(same apps.out), only one time succeed, please check the log

(Please visit the site to view this file)

Part Number:AM3351

Tool/software: Linux

Hi,

I am working on AM335x with SARA-R412M GSM module. I done code implementaion, But, I unable to on the GSM module. If anyone experience Please provide the fix.

Please find the attached log,

Jan 1 00:00:00 txsky2 user.info gsmInit: GSM modem initialization
Jan 1 00:00:02 txsky2 user.debug gsmInit: Run power on initialization
Jan 1 00:00:13 txsky2 user.debug gsmInit: Load Multiplexer
Jan 1 00:00:13 txsky2 user.info gsmInit: Loading multiplexer initialization

<After Some time>

Jan 1 00:01:30 txsky2 daemon.warn systemd[1]: gsmInit.service: Start operation timed out. Terminating.
Jan 1 00:01:30 txsky2 daemon.notice systemd[1]: gsmInit.service: Unit entered failed state.
Jan 1 00:01:30 txsky2 daemon.warn systemd[1]: gsmInit.service: Failed with result 'timeout'.
Jan 1 00:01:30 txsky2 daemon.info systemctl[342]: Job for gsmInit.service failed because a timeout was exceeded.
Jan 1 00:01:30 txsky2 daemon.info systemctl[342]: See "systemctl status gsmInit.service" and "journalctl -xe" for details.

Thanks & Regards,

VinothS

Part Number:TDA3XEVM

Tool/software: TI-RTOS

Hi,

I noticed EMIF tools from ti which will generate the register values for TDA3x, In step-2 Board details, How to find the trace lengths for the custom ddr conected to EMIF1? Could you please help on to get the values?

Regards

Prakash

Part Number:66AK2G12

Hello,

My customer has a problem with USB Compliance Test on their custom board using K2G. It seems they failed in jitter requirement. 
They are generating USB clock via UART PLL (384Mhz output). This output has been divided by 16 (via BOOTCFG_USB0_CLKCTL ) to generate 24Mhz USB core clock.

From my understanding, maximizing VCO in PLL is needed in general in order to minimize the related clock jitter. Actually, TRM says :

Once the ROM boot is complete, reconfiguring the PLL with the intention of optimizing and
reducing output jitter may optionally be done, even if the PLL is already configured by the
ROM code. To minimize the overall output jitter, the PLL VCO output must be operated close
to, but not above, the maximum operating frequency of 4.2 GHz. Maximizing the VCO
frequency within the PLL is done by setting the PLL Output Divider as close as possible to
15 (OUTPUT_DIVIDE+1 must be an even number only). The PLLD value must be kept at 0
or as low as possible. The target PLLOUT frequency is therefore achieved by adjusting
PLLM.
PLL VCO Frequency = CLKIN / (PLLD+1) × (PLLM+1)
PLL OUT Frequency = VCO / (OUTPUT_DIVIDE+1)

So, I would like the customer to try maximizing VCO, but my question here is, the max VCO is really allowed up to 4.2Ghz. I feel that is pretty high. Could you comment ?

Best Regards,
NK

Support Guidance for C5416, C5502, C5504, C5505, C5509A, C5510A, C5514, C5515, C5532, C5533, C5534, C5535.

Q: I’m developing an application based on TI’s C5000 family of digital signal processors and saw that these were recently listed as NRND. I have some questions and need some support. Can you help me? Do you have alternatives to these processors?

A: Thanks for reaching out. The parts mentioned above are not recommended for new designs (NRND) and will have very limited support from TI, but will continue to be in production to support existing customers*. While not a direct replacement we currently support the TMS320C5517 DSP, as part of the C5000 low-power DSP family. You may also want to consider evaluating a C6000 fix and floating point DSPs as a migration path. While they are not direct replacements for the various C5000 DSPs, we recommend evaluating the following devices(s) as potential alternatives:

• TMS320C5517:http://www.ti.com/product/TMS320C5517

• TMS320C6742: http://www.ti.com/product/TMS320C6742

• TMS320C6743: http://www.ti.com/product/TMS320C6743

• TMS320C6745: http://www.ti.com/product/TMS320C6745

• TMS320C6746: http://www.ti.com/product/TMS320C6746

•  TMS320C6747:http://www.ti.com/product/TMS320C6747

• TMS320C6748:http://www.ti.com/product/TMS320C6748
  

  Should you choose to continue your design with the C5000 DSPs, see below for product information and additional resources:

• Each device’s product folder on TI.com includes more information on the part and lists available documentation and software:

  • C5416: http://www.ti.com/product/TMS320VC5416

  • C5502: http://www.ti.com/product/TMS320C5502

  • C5504: http://www.ti.com/product/TMS320C5504

  • C5505: http://www.ti.com/product/TMS320C5505

  • C5509A: http://www.ti.com/product/TMS320VC5509A

  • C5510A: http://www.ti.com/product/TMS320VC5510A

  • C5514: http://www.ti.com/product/TMS320C5514

  • C5515: http://www.ti.com/product/TMS320C5515

  • C5532: http://www.ti.com/product/TMS320C5532

  • C5533: http://www.ti.com/product/TMS320C5533

  • C5534: http://www.ti.com/product/TMS320C5534

  • C5535: http://www.ti.com/product/TMS320C5535

     You may also search the E2E forums for archived posts of previous discussions which may help address your questions.

     Finally, for additional design support for your C5000 applications design, you can reach out to one of the following third parties:

     Adaptive Digital Technology

    http://www.adaptivedigital.com

    brian.mcCarthy@adaptivedigital.com

Part Number:PROCESSOR-SDK-AM335X

Tool/software: Linux

Hello,

I need help with using azure-iot-sdk-c on the am335x. I am using am335x starter kit and i need to know how can i import library dependencies and header files for azure iot hub. I tried copying over the files to the filesystem but it couldn't boot up the device properly. Can someone point me to some materials or examples for working with Azure SDK on am335x. 

Part Number:IWR1443BOOST

Tool/software: Code Composer Studio

Hello,

Im using the IWR1443 Boost radar sensor togehter with TSW1400_board and the mmWave DevPack  to capture the raw data.

Now I want to set my duty Cycle in the Radar Studio GUI to 100%. So that I have a countinous stream(lets say 2.5 seconds) of Chirps with out interleaving time between the frames.

For example with following Settings

Slope=25.009e12
adcSamples=256
tChirp=80e-6
tIdle=10e-6
period=11.52e-3
noFrames=250
noChirps=128

I tried this settings but i cant start my measurment.

Now my question is. Is it possible to set the Duty Cyle to 100% ?

Best regards,

Patrick

Part Number:AM3352

Tool/software: Linux

Hi champs

I know in the TRM it indicates that SYSBOOT pins [11:6]  are dont care if we use boot mode 11100b. What i am worried about is that in all the TI platforms we pull all the sysboot pins either high or low no matter what boot mode we use. So i am trying to double check  to make sure that those sysboot pins can be left floating.

Also if i use pins U1 and U2 for uart2 CTS and RTS do i have to pull them high or low because they are used as sysboot pins when the processor boots? I know that the sysboot pins are read on the rising edge of the reset but if these are don't care then it should not matter correct?

We are seeing some strange behavior from a customer board and trying to see what can cause the strange behavior.

Thanks

Regards

Mohsen 

Part Number:66AK2E05

Tool/software: Linux

Hi community,

Im working on Keystone K2E EVM. I downloaded Processor-SDK-Linux-RT-K2E. I want to run one Core Linux with a custom configuration, but i failed. I get these 2 errors:

Internal error: Oops: 206 [#1] PREEMPT SMP ARM

Kernel Panic (Unable to handle kernel paging request at virtual address)

Im using a custom uboot, there is no bootargs available in uboot environment in this uboot configuration. When i use prebuild-images, i see only "Uncompressing Linux... done, booting the kernel.". I think kernel hangs on booting, but i cant see where because of bootargs not available(therefore no earlyprintk available too). So i recompiled linux kernel.

I want to create a zImage completely undepended from uboot, bootargs etc. So, i changed this rows inside 'arch/arm/configs/tisdk_k2e-evm-rt_defconfig' to;

# CONFIG_CMDLINE_PARTITION is not set
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_FB_CMDLINE is not set
CONFIG_CMDLINE="console=ttyS0,115200n8 rootwait=1 earlyprintk root=/dev/ram0 rw"
# CONFIG_BLK_CMDLINE_PARSER is not set
CONFIG_TTY_PRINTK=y
CONFIG_CMA_SIZE_MBYTES=192
CONFIG_PAGE_OFFSET=0xD0000000
CONFIG_BLK_DEV_RAM_COUNT=16

CONFIG_NR_CPUS=1 for One Core Linux

And

all **_DEBUG_** lines set to '=y'

I want to remap footprint from default(0x80000000-0xC0000000) to (0xD0000000-0xF8000000). So i changed

'arch/arm/boot/dts/keystone.dtsi' inside;

'memory {reg = <0x00000000 0xD0000000 0x00000000 0x28000000>;};'

' soc {...; ranges = <0x0 0x0 0x0 0xFFFFFFFF>; dma-ranges = <0xD0000000 0x8 0x00000000 0x28000000>; ...}'

'arch/arm/boot/dts/keystone-k2e.dtsi' inside;

remove cpu@1, cpu@2, cpu@3 for Once Core Linux

'arch/arm/Kconfig' inside;

PAGE_OFFSET 0x80000000 to 0xD0000000

With above configuration(conf1), kernel hangs on boot. I think i missed some address configuration for remapping. Here is the output;

Uncompressing Linux... done, booting the kernel.
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.14.79-rt47-ga72bf1418c (srt@ubuntu) (gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #1 SMP PREEMPT RT Tue Jul 9 05:43:17 PDT 2019
[ 0.000000] CPU: ARMv7 Processor [412fc0f4] revision 4 (ARMv7), cr=30c5387d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] OF: fdt: Machine model: Texas Instruments Keystone 2 Edison EVM
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm/mm/physaddr.c:42 __virt_to_phys+0xc4/0xc8
[ 0.000000] virt_to_phys used for non-linear address: f0000000 (0xf0000000)
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.14.79-rt47-ga72bf1418c #1
[ 0.000000] Hardware name: Keystone
[ 0.000000] Backtrace:
[ 0.000000] [<d020c4f4>] (dump_backtrace) from [<d020c7d8>] (show_stack+0x18/0x1c)
[ 0.000000] r7:600001d3 r6:d106aa44 r5:00000000 r4:d106aa44
[ 0.000000] [<d020c7c0>] (show_stack) from [<d09a65f0>] (dump_stack+0x80/0x94)
[ 0.000000] [<d09a6570>] (dump_stack) from [<d021fe00>] (__warn+0xec/0x104)
[ 0.000000] r7:00000009 r6:d0bbbcf0 r5:00000000 r4:d1001e68
[ 0.000000] [<d021fd14>] (__warn) from [<d021fe58>] (warn_slowpath_fmt+0x40/0x48)
[ 0.000000] r9:00000000 r8:ffffffff r7:00000000 r6:7fffffff r5:d0e46278 r4:d0bbbcb8
[ 0.000000] [<d021fe1c>] (warn_slowpath_fmt) from [<d0218a3c>] (__virt_to_phys+0xc4/0xc8)
[ 0.000000] r3:f0000000 r2:d0bbbcb8
[ 0.000000] r4:f0000000
[ 0.000000] [<d0218978>] (__virt_to_phys) from [<d0e2da0c>] (early_init_fdt_reserve_self+0x28/0x4c)
[ 0.000000] r9:d1014ac0 r8:d1083e88 r7:d1001fc4 r6:d1083e8c r4:d1a6f4c8
[ 0.000000] [<d0e2d9e4>] (early_init_fdt_reserve_self) from [<d0e06a58>] (arm_memblock_init+0x174/0x1b8)
[ 0.000000] r4:d0200000
[ 0.000000] [<d0e068e4>] (arm_memblock_init) from [<d0e04628>] (setup_arch+0x5f0/0xbf8)
[ 0.000000] r10:d1083f80 r9:d1014ac0 r8:d0e45a48 r7:d1001fc4 r6:d0008000 r5:d0e3d270
[ 0.000000] r4:d1a79148
[ 0.000000] [<d0e04038>] (setup_arch) from [<d0e00a3c>] (start_kernel+0x68/0x404)
[ 0.000000] r10:00000000 r9:412fc0f4 r8:d100fe80 r7:d1014c38 r6:00000000 r5:d100fe98
[ 0.000000] r4:00000000
[ 0.000000] [<d0e009d4>] (start_kernel) from [<d0008090>] (0xd0008090)
[ 0.000000] r10:00000000 r9:412fc0f4 r8:d0007000 r7:d1014c38 r6:d0e45a44 r5:d100fe98
[ 0.000000] r4:d10840d4
[ 0.000000] ---[ end trace 0000000000000001 ]---
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000081f800000, size 8 MiB
[ 0.000000] OF: reserved mem: initialized node dsp-common-memory@81f800000, compatible id shared-dma-pool
[ 0.000000] cma: dma_contiguous_reserve(limit 4fffffff)
[ 0.000000] cma: dma_contiguous_reserve: reserving 192 MiB for global area
[ 0.000000] cma: cma_declare_contiguous(size 0x000000000c000000, base 0x0000000000000000, limit 0x000000014fffffff alignment 0x0000000000000000)
[ 0.000000] cma: Reserved 192 MiB at 0x00000000e4000000
[ 0.000000] On node 0 totalpages: 163840
[ 0.000000] free_area_init_node: node 0, pgdat d106ac40, node_mem_map e39f8000
[ 0.000000] DMA zone: 1152 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 131072 pages, LIFO batch:31
[ 0.000000] HighMem zone: 32768 pages, LIFO batch:7
[ 0.000000] Unable to handle kernel paging request at virtual address f0000000
[ 0.000000] pgd = d0003000
[ 0.000000] [f0000000] *pgd=800000d0007003, *pmd=00000000
[ 0.000000] Internal error: Oops: 206 [#1] PREEMPT SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 4.14.79-rt47-ga72bf1418c #1
[ 0.000000] Hardware name: Keystone
[ 0.000000] task: d1012d80 task.stack: d1000000
[ 0.000000] PC is at fdt_check_header+0xc/0x80
[ 0.000000] LR is at __unflatten_device_tree+0x74/0x2b0
[ 0.000000] pc : [<d09a67ac>] lr : [<d07ec7b8>] psr: 600000d3
[ 0.000000] sp : d1001ec0 ip : d1001ed0 fp : d1001ecc
[ 0.000000] r10: 00000000 r9 : d1a6f4b0 r8 : 00000000
[ 0.000000] r7 : d0e2c9c4 r6 : f0000000 r5 : d0e3d270 r4 : d1077460
[ 0.000000] r3 : 00000000 r2 : d1a6f4b0 r1 : 00000000 r0 : f0000000
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment user
[ 0.000000] Control: 30c5387d Table: d0003000 DAC: fffffffd
[ 0.000000] Process swapper (pid: 0, stack limit = 0xd1000210)
[ 0.000000] Stack: (0xd1001ec0 to 0xd1002000)
[ 0.000000] 1ec0: d1001efc d1001ed0 d07ec7b8 d09a67ac d0e2c9c4 d0e2c9c4 d0e3d270 d1599520
[ 0.000000] 1ee0: d0000000 00000000 d1014ac0 d1083f80 d1001f1c d1001f00 d0e2db2c d07ec750
[ 0.000000] 1f00: 00000000 d1001f10 d0227638 d1012a40 d1001fa4 d1001f20 d0e049b0 d0e2dafc
[ 0.000000] 1f20: 00000000 00000000 00000000 00000000 ffffffff d1001f40 d027f080 d0e3d270
[ 0.000000] 1f40: fffff000 d1024020 00000000 f7ffffff d0280544 d027f064 d0000000 00000000
[ 0.000000] 1f60: 00000000 d100fe98 00000000 d1014c38 d1001f94 d1001f80 d027fce8 00000000
[ 0.000000] 1f80: d100fe98 00000000 d1014c38 d100fe80 412fc0f4 00000000 d1001ff4 d1001fa8
[ 0.000000] 1fa0: d0e00a3c d0e04044 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.000000] 1fc0: 00000000 d0e45a48 00000000 d10840d4 d100fe98 d0e45a44 d1014c38 d0007000
[ 0.000000] 1fe0: 412fc0f4 00000000 00000000 d1001ff8 d0008090 d0e009e0 00000000 00000000
[ 0.000000] Backtrace:
[ 0.000000] [<d09a67a0>] (fdt_check_header) from [<d07ec7b8>] (__unflatten_device_tree+0x74/0x2b0)
[ 0.000000] [<d07ec744>] (__unflatten_device_tree) from [<d0e2db2c>] (unflatten_device_tree+0x3c/0x4c)
[ 0.000000] r10:d1083f80 r9:d1014ac0 r8:00000000 r7:d0000000 r6:d1599520 r5:d0e3d270
[ 0.000000] r4:d0e2c9c4 r3:d0e2c9c4
[ 0.000000] [<d0e2daf0>] (unflatten_device_tree) from [<d0e049b0>] (setup_arch+0x978/0xbf8)
[ 0.000000] r4:d1012a40
[ 0.000000] [<d0e04038>] (setup_arch) from [<d0e00a3c>] (start_kernel+0x68/0x404)
[ 0.000000] r10:00000000 r9:412fc0f4 r8:d100fe80 r7:d1014c38 r6:00000000 r5:d100fe98
[ 0.000000] r4:00000000
[ 0.000000] [<d0e009d4>] (start_kernel) from [<d0008090>] (0xd0008090)
[ 0.000000] r10:00000000 r9:412fc0f4 r8:d0007000 r7:d1014c38 r6:d0e45a44 r5:d100fe98
[ 0.000000] r4:d10840d4
[ 0.000000] Code: e89da800 e1a0c00d e92dd800 e24cb004 (e5903000)
[ 0.000000] ---[ end trace 0000000000000002 ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!

When i changed footprint back from (0xD0000000-0xF8000000) to (0x80000000-0xFFFFFFFF)

'arch/arm/boot/dts/keystone.dtsi' inside;

'memory {reg = <0x00000000 0x80000000 0x00000000 0x80000000>;};'

' soc {...; ranges = <0x0 0x0 0x0 0xFFFFFFFF>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; ...}'

With (0x80000000-0xFFFFFFFF) mapping configuration(conf2), Kernel hangs on a little bit forward stage. Here is the output;

Uncompressing Linux... done, booting the kernel.
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.14.79-rt47-ga72bf1418c (srt@ubuntu) (gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #1 SMP PREEMPT RT Tue Jul 9 03:07:27 PDT 2019
[ 0.000000] CPU: ARMv7 Processor [412fc0f4] revision 4 (ARMv7), cr=30c5387d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] OF: fdt: Machine model: Texas Instruments Keystone 2 Edison EVM
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000081f800000, size 8 MiB
[ 0.000000] OF: reserved mem: initialized node dsp-common-memory@81f800000, compatible id shared-dma-pool
[ 0.000000] cma: Reserved 64 MiB at 0x00000000eb000000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: Using PSCI v0.1 Function IDs from DT
[ 0.000000] percpu: Embedded 17 pages/cpu @ea90e000 s37356 r8192 d24084 u69632
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 190820
[ 0.000000] Kernel command line: console=ttyS0,115200n8 rootwait=1 earlyprintk root=/dev/ram0 rw
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 10, 4718592 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 667412K/770048K available (8192K kernel code, 485K rwdata, 2844K rodata, 2048K init, 10196K bss, 28908K reserved, 73728K cma-reserved, 0K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xef800000 - 0xff800000 ( 256 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef000000 ( 752 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0a00000 (10208 kB)
[ 0.000000] .init : 0xc0e00000 - 0xc1000000 (2048 kB)
[ 0.000000] .data : 0xc1000000 - 0xc10797d0 ( 486 kB)
[ 0.000000] .bss : 0xc1084378 - 0xc1a79688 (10197 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1.
[ 0.000000] RCU priority boosting: priority 1 delay 500 ms.
[ 0.000000] RCU debug extended QS entry/exit.
[ 0.000000] No expedited grace period (rcu_normal_after_boot).
[ 0.000000] Tasks RCU enabled.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] kmemleak: Kernel memory leak detector disabled
[ 0.000000] arch_timer: cp15 timer(s) running at 233.33MHz (virt).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x6ba0ac50b7, max_idle_ns: 881590427583 ns
[ 0.000004] sched_clock: 56 bits at 233MHz, resolution 4ns, wraps every 4398046511102ns
[ 0.000009] Switching to timer-based delay loop, resolution 4ns
[ 0.000214] keystone timer clock @233333333 Hz
[ 0.000512] Console: colour dummy device 80x30
[ 0.269839] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.269841] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.269844] ... MAX_LOCK_DEPTH: 48
[ 0.269846] ... MAX_LOCKDEP_KEYS: 8191
[ 0.269847] ... CLASSHASH_SIZE: 4096
[ 0.269850] ... MAX_LOCKDEP_ENTRIES: 32768
[ 0.269851] ... MAX_LOCKDEP_CHAINS: 65536
[ 0.269853] ... CHAINHASH_SIZE: 32768
[ 0.269855] memory used by lock dependency info: 4639 kB
[ 0.269857] per task-struct memory footprint: 1536 bytes
[ 0.269891] kmemleak: Early log buffer exceeded (1066), please increase DEBUG_KMEMLEAK_EARLY_LOG_SIZE
[ 0.270836] Calibrating delay loop (skipped), value calculated using timer frequency.. 466.66 BogoMIPS (lpj=2333333)
[ 0.270843] pid_max: default: 32768 minimum: 301
[ 0.271173] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.271185] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.273100] CPU: Testing write buffer coherency: ok
[ 0.273149] CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
[ 0.273736] /cpus/cpu@0 missing clock-frequency property
[ 0.382750] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.421311] Setting up static identity map for 0xc0200000 - 0xc0200138
[ 0.441174] Hierarchical SRCU implementation.
[ 0.504437] EFI services will not be available.
[ 0.541427] smp: Bringing up secondary CPUs ...
[ 0.546090] smp: Brought up 1 node, 1 CPU
[ 0.550226] SMP: Total of 1 processors activated (466.66 BogoMIPS).
[ 0.556639] CPU: All CPU(s) started in SVC mode.
[ 0.563241] devtmpfs: initialized
[ 0.611020] random: get_random_u32 called from bucket_table_alloc+0x158/0x298 with crng_init=0
[ 0.621724] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[ 0.635099] DMA-API: preallocated 4096 debug entries
[ 0.640199] DMA-API: debugging enabled by kernel config
[ 0.646500] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.656578] futex hash table entries: 256 (order: 3, 32768 bytes)
[ 0.663133] ------------[ cut here ]------------
[ 0.667892] WARNING: CPU: 0 PID: 1 at mm/cma.c:111 cma_init_reserved_areas+0xb4/0x274
[ 0.675890] Modules linked in:
[ 0.679073] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.14.79-rt47-ga72bf1418c #1
[ 0.679075] Hardware name: Keystone
[ 0.679077] Backtrace:
[ 0.679088] [<c020c500>] (dump_backtrace) from [<c020c7e4>] (show_stack+0x18/0x1c)
[ 0.679093] r7:60000013 r6:c106ad44 r5:00000000 r4:c106ad44
[ 0.679105] [<c020c7cc>] (show_stack) from [<c09a90b0>] (dump_stack+0x80/0x94)
[ 0.679112] [<c09a9030>] (dump_stack) from [<c021fdd8>] (__warn+0xec/0x104)
[ 0.679116] r7:00000009 r6:c0bd2d5c r5:00000000 r4:00000000
[ 0.679122] [<c021fcec>] (__warn) from [<c021fea8>] (warn_slowpath_null+0x28/0x30)
[ 0.679126] r9:c106cc8f r8:00000000 r7:c1084380 r6:c159b618 r5:c159b618 r4:0081f800
[ 0.679133] [<c021fe80>] (warn_slowpath_null) from [<c0e166c0>] (cma_init_reserved_areas+0xb4/0x274)
[ 0.679140] [<c0e1660c>] (cma_init_reserved_areas) from [<c02018c8>] (do_one_initcall+0x4c/0x16c)
[ 0.679145] r10:c0e46858 r9:c1084380 r8:c0e4683c r7:c1084380 r6:c0e1660c r5:00000000
[ 0.679147] r4:ffffe000
[ 0.679153] [<c020187c>] (do_one_initcall) from [<c0e01040>] (kernel_init_freeable+0x268/0x300)
[ 0.679157] r8:c0e4683c r7:c1084380 r6:00000002 r5:c0e61030 r4:c0cc5a5c
[ 0.679163] [<c0e00dd8>] (kernel_init_freeable) from [<c09bcfe4>] (kernel_init+0x10/0x120)
[ 0.679168] r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09bcfd4
[ 0.679170] r4:00000000
[ 0.679178] [<c09bcfd4>] (kernel_init) from [<c0208720>] (ret_from_fork+0x14/0x34)
[ 0.679181] r5:c09bcfd4 r4:00000000
[ 0.679183] ---[ end trace 0000000000000001 ]---
[ 0.822456] Unable to handle kernel paging request at virtual address fb2aa000
[ 0.829833] pgd = c0003000
[ 0.832654] [fb2aa000] *pgd=800000c0007003, *pmd=00000000
[ 0.838208] Internal error: Oops: 206 [#1] PREEMPT SMP ARM
[ 0.838211] Modules linked in:
[ 0.838217] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 4.14.79-rt47-ga72bf1418c #1
[ 0.838220] Hardware name: Keystone
[ 0.838223] task: ea058000 task.stack: ea054000
[ 0.838229] PC is at cma_init_reserved_areas+0xf8/0x274
[ 0.838232] LR is at __warn+0xb4/0x104
[ 0.838236] pc : [<c0e16704>] lr : [<c021fda0>] psr: 60000013
[ 0.838239] sp : ea055e90 ip : ea93c000 fp : ea055edc
[ 0.838241] r10: 00000000 r9 : c106cc8f r8 : 00000000
[ 0.838244] r7 : c0bd2d5c r6 : c159b618 r5 : 0081f800 r4 : 0081f800
[ 0.838247] r3 : 1096e000 r2 : 000003c0 r1 : 00000024 r0 : 0075f800
[ 0.838252] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
[ 0.838255] Control: 30c5387d Table: c0003000 DAC: fffffffd
[ 0.838258] Process swapper/0 (pid: 1, stack limit = 0xea054210)
[ 0.838261] Stack: (0xea055e90 to 0xea056000)
[ 0.838265] 5e80: c02ef684 c159b618 c159b618 014080c0
[ 0.838270] 5ea0: c1012ac4 c1598d80 00000000 00000002 c1084380 ffffe000 00000000 c0e1660c
[ 0.838275] 5ec0: c1084380 c0e4683c c1084380 c0e46858 ea055f4c ea055ee0 c02018c8 c0e16618
[ 0.838279] 5ee0: ea055f04 ea055ef0 c027af00 c0bbff98 c0bbff78 c0bbffc4 c0bd31b8 00000000
[ 0.838283] 5f00: c0bbff0c c0c676e4 00000001 00000001 c106d368 c0cc5a5c eafffdfd 00000000
[ 0.838287] 5f20: c10191b0 c0cc5a5c 00000002 c0cc5a5c c0e61030 00000002 c1084380 c0e4683c
[ 0.838291] 5f40: ea055f94 ea055f50 c0e01040 c0201888 00000001 00000001 00000000 c0e00644
[ 0.838295] 5f60: c0e00644 000000e8 00000000 00000000 c09bcfd4 00000000 00000000 00000000
[ 0.838298] 5f80: 00000000 00000000 ea055fac ea055f98 c09bcfe4 c0e00de4 00000000 c09bcfd4
[ 0.838302] 5fa0: 00000000 ea055fb0 c0208720 c09bcfe0 00000000 00000000 00000000 00000000
[ 0.838306] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.838310] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[ 0.838312] Backtrace:
[ 0.838320] [<c0e1660c>] (cma_init_reserved_areas) from [<c02018c8>] (do_one_initcall+0x4c/0x16c)
[ 0.838326] r10:c0e46858 r9:c1084380 r8:c0e4683c r7:c1084380 r6:c0e1660c r5:00000000
[ 0.838328] r4:ffffe000
[ 0.838333] [<c020187c>] (do_one_initcall) from [<c0e01040>] (kernel_init_freeable+0x268/0x300)
[ 0.838338] r8:c0e4683c r7:c1084380 r6:00000002 r5:c0e61030 r4:c0cc5a5c
[ 0.838342] [<c0e00dd8>] (kernel_init_freeable) from [<c09bcfe4>] (kernel_init+0x10/0x120)
[ 0.838347] r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c09bcfd4
[ 0.838349] r4:00000000
[ 0.838355] [<c09bcfd4>] (kernel_init) from [<c0208720>] (ret_from_fork+0x14/0x34)
[ 0.838358] r5:c09bcfd4 r4:00000000
[ 0.838363] Code: e34c70bd e50b5044 e1a05004 e50b6048 (e79c3003)
[ 1.102100] ---[ end trace 0000000000000002 ]---
[ 1.106848] Kernel panic - not syncing: Fatal exception
[ 1.112215] ---[ end Kernel panic - not syncing: Fatal exception
[ 2.343849] workqueue: round-robin CPU selection forced, expect performance impact

I cant boot kernel with a specific memory range(0xD0000000-0xF8000000), not boot with bigger range (0x80000000-0xFFFFFFFF) too with different reason.

I tried a lot of ways and research from a lot of websites, but cant find a solution. Same error for both configuration is "Unable to handle kernel paging request at virtual address ********, pgd = 0xD0003000". I noticed that the 0xD0003000 address is the first function RAM address in 'System.map'. Is it possible to kernel can not reach RAM addresses? Can i use directly phsical mapping instead of virtual mapping?

00000024 A cpu_ca15_suspend_size
00000024 A cpu_v7_bpiall_suspend_size
00000024 A cpu_v7_suspend_size
0000002c A cpu_ca9mp_suspend_size
d0003000 A swapper_pg_dir
d0008000 T _text
d0008000 T stext

How can i boot kernel with specific memory ranges and independently from uboot? By the way, i run linux with below steps on CCSv6;

Connecting ARM Core 0,

Load zImage to DDR(specified memory range start addr(if conf1: 0xD0000000, if conf2: 0x80000000),

Load keystone-k2e-evm.dtb to DDR (specified memory range area (if conf1: 0xF0000000, if conf2: 0x87000000)),

PC: zImage Load Addr,

R0: 0x00000000,

R1: 0xFFFFFFFF,

R2: keystone-k2e-evm.dtb Load Addr,

Run ARM Core 0

Thank you,

Best Regards,

Srt