Part Number:AM6548

Hi, TI engineers

Today  I met some questions when I read the AM654x's datasheet.

As the datasheet said(the blue part as below),

does it means that the NAVSS probably has two function, one is for DMA, the other one is for Interprocessor Communication?

does it have other function as well?

and I can't understand a sentence(the red as below) clearly, would you please make a explanation for me?

Best Regards

Hope Chen

6.9 Interprocessor Communication
6.9.1 NAVSS
NAVSS specifies the data structures used by Texas Instruments standard communications modules to
facilitate direct memory access (DMA) and to provide a consistent application programming interface (API)
to the host software in multi-core devices. The data structures and the API used to manipulate them will
be jointly referred to as NAVSS.
Frequent tasks are commonly offloaded from the host processor to peripheral hardware to increase
system performance. Significant performance gains may result from careful design of the host software
and communication module interface. In networking systems, packet transmission and reception are
critical tasks. Texas Instruments has developed the NAVSS standard, which is aimed at maximizing the
efficiency of interaction between the host software and communications modules.

Part Number:66AK2H14

Tool/software: TI-RTOS

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Log.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Clock.h>

#include <ti/sysbios/hal/Core.h>
#include <ti/sysbios/family/c64p/MemoryProtect.h>
#include <ti/sysbios/family/c64p/Exception.h>
#include <ti/sysbios/family/c66/Cache.h>

#include <c6x.h>
#include <string.h>

#include <func.h>

/* define */
#define XMC_BASE_ADDR       (0x8000000)
#define XMPAX2_L            (*(Uint32*) XMC_BASE_ADDR + 0x10)
#define XMPAX2_R            (*(Uint32*) XMC_BASE_ADDR + 0x14)

/* MPAX registers configuration */
Uint32 *xmpax2l_addr = NULL;
Uint32 *xmpax2r_addr = NULL;

/*
 *  ======== mem_protectFxn ========
 */
Void mem_protectFxn(UArg a0, UArg a1)
{
    /* Address initialization of MPAX register */
    xmpax2l_addr = (Uint32*)XMPAX2_L;
    xmpax2r_addr = (Uint32*)XMPAX2_R;

    /* Set MPAX registers */
    *xmpax2l_addr = 0x121010FF; // replacement address + permissions (FF, all accesses allowed)
    *xmpax2r_addr= 0x2101000B; // base address + segment size: B, 4KB

    System_flush(); /* force SysMin output to console */
}

/*
 *  ======== main ========
 */
Int main()
{
    System_printf("enter main()\n");
    BIOS_start();    /* does not return */
    return(0);
}

Part Number:TMS320C6678

Tool/software: TI-RTOS

Hi,

I would like to create a non-cacheable memory section in the shared memory (MSMC SRAM). I do know about the memory attribute registers. However, there only is only one MAR covering the whole MSMC SRAM (I would like to only have a small non-cacheable section). I therefore looked into the TI linalg platform (ti/linalg_1_2_0_0/packages/ti/linalg/platforms/evm6678), which reads as

/*
 * Description of Memory Regions used by the OMP runtime
 *
 * L2SRAM               Local Level 2 (64K of L2 configured as SRAM)
 * MSMCSRAM             Shared Level 2 internal (MCMC configured as level 2 
 *                      memory, cached in L1)
 * MSMCSRAM_NOCACHE     Shared Level 1 internal (MSMC configured as level 1 
 *                      memory i.e. it is not cached)
 */
metaonly module Platform inherits xdc.platform.IPlatform {

    config ti.platforms.generic.Platform.Instance CPU =
        ti.platforms.generic.Platform.create("CPU", {
            clockRate:      1000,                                       
            catalogName:    "ti.catalog.c6000",
            deviceName:     "TMS320C6678",
            customMemoryMap: [
                ["L2SRAM",    
                                {name: "L2SRAM",  base: 0x00800000, 
                                len: 0x00060000, access: "RW"}],
                ["OMP_MSMC_NC_VIRT",   
                                {name: "OMP_MSMC_NC_VIRT", base: 0xA0000000, 
                                len: 0x00020000, access: "RW"}],
                ["OMP_MSMC_NC_PHY",   
                               {name: "OMP_MSMC_NC_PHY", base: 0x0C000000, 
                                len: 0x00020000, access: "RW"}],
                ["MSMCSRAM",   
                                {name: "MSMCSRAM", base: 0x0C020000, 
                                len: 0x003E0000, access: "RWX"}],
                ["DDR3",   
                                {name: "DDR3", base: 0x80000000, 
                                len: 0x20000000, access: "RWX"}], /* C6678 EVM has only 512 MB DDR3 */
            ],
            l2Mode:"128k",
            l1PMode:"32k",
            l1DMode:"32k",
    });

- Am I right to assume that access: "RW" means read-write and access: "RWX" means read-write-cache?

I then created my platform package (tried both two ways, platform wizard and manually), and defined a MSMCSRAMNC memory map with access: "RW" (just as above), created a custom memory section in the linker command file

.nocache_section > MSMCSRAMNC

and threw some variables inside like

#pragma DATA_SECTION (request_1, ".nocache_section");
volatile uint8_t request_1 = 0;
#pragma DATA_SECTION (acknowledge_1, ".nocache_section");
volatile uint8_t acknowledge_1 = 0;

Everything builds, runs fine but the variables are still being cached.

- How does the linalg package achieve to get a non-cacheable section there? I do know about CacheDis/Enable functions from the chip support library. However, this would only work for the whole shared memory because MAR12 spans the whole shared memory. Moreover, it seems like I can't disable the cache for MAR12. So, how does the linalg library do this?

Thanks a lot,

Idris

Part Number:TDA2PXEVM

Tool/software: Linux

Hi:

   In visionSDK, we want to configure the ivi-shell for weston, but seems the weston not read the /etc/weston.ini

root@dra7xx-evm:~# cat /etc/weston.ini
[core]
shell=ivi-shell.so

[ivi-shell]
ivi-module=hmi-controller.so
ivi-shell-user-interface=/usr/libexec/weston-ivi-shell-user-interface

base-layer-id=1000
workspace-background-layer-id=2000
workspace-layer-id=3000
application-layer-id=4000


background-icon=/usr/share/weston/background.png
background-id=1001
panel-icon=/usr/share/weston/panel.png
panel-id=1002
tiling-icon=/usr/share/weston/tiling.png
tiling-id=1003
sidebyside-icon=/usr/share/weston/sidebyside.png
sidebyside-id=1004
fullscreen-icon=/usr/share/weston/fullscreen.png
fullscreen-id=1005
random-icon=/usr/share/weston/random.png
random-id=1006
home-icon=/usr/share/weston/home.png
home-id=1007
workspace-background-color=0x99000000
workspace-background-id=2001


[ivi-launcher]
workspace-id=0
icon-id=4001
icon=/usr/share/weston/icon_ivi_flower.png
path=/usr/bin/weston-flower


[ivi-launcher]
workspace-id=1
icon-id=4003
icon=/usr/share/weston/icon_ivi_simple-egl.png
path=/usr/bin//weston-simple-egl

[ivi-launcher]
workspace-id=1
icon-id=4004
icon=/usr/share/weston//icon_ivi_simple-shm.png
path=/usr/bin/weston-simple-shm

[screensaver]
# Uncomment path to disable screensaver
#path=@libexecdir@/weston-screensaver

root@dra7xx-evm:~# cat /var/log/weston.log 
Date: 2018-09-17 UTC
[09:22:46.553] weston 1.9.0
               http://wayland.freedesktop.org
               Bug reports to: bugs.freedesktop.org/enter_bug.cgi
               Build: 1.8.93-2-gb05cdb8 configure.ac: bump to version 1.9.0 for the official release (2015-09-21 18:11:26 -0700)
[09:22:46.553] OS: Linux, 4.4.84, #1 SMP PREEMPT Thu Jul 4 03:14:32 PDT 2019, armv7l
malformed section header: [core]

[09:22:46.558] Starting with no config file.
[09:22:46.565] Loading module '/usr/lib/weston/drm-backend.so'
[09:22:46.600] Output repaint window is 7 ms maximum.
[09:22:46.600] initializing drm backend
[09:22:46.601] using /dev/dri/card0
[09:22:46.602] Loading module '/usr/lib/weston/gl-renderer.so'
loaded module : gbm_pvr.so
found valid GBM backend : gbm_pvr.so
[09:22:46.668] warning: either no EGL_EXT_platform_base support or specific platform support; falling back to eglGetDisplay.
[09:22:46.678] warning: EGL_EXT_buffer_age not supported. Performance could be affected.
[09:22:46.678] Retrieving EGL client extension string failed.
[09:22:46.678] warning: no input devices on entering Weston. Possible causes:
        - no permissions to read /dev/input/event*
        - seats misconfigured (Weston backend option 'seat', udev device property ID_SEAT)
[09:22:46.678] failed to create input devices
[09:22:46.712] EGL version: 1.4 build 1.14@3699939 (MAIN)
[09:22:46.712] EGL vendor: Imagination Technologies
[09:22:46.712] EGL client APIs: OpenGL_ES 
[09:22:46.712] EGL extensions: EGL_IMG_client_api_ogl EGL_KHR_image
               EGL_KHR_image_base EGL_KHR_gl_texture_2D_image
               EGL_KHR_gl_texture_cubemap_image EGL_KHR_gl_renderbuffer_image
               EGL_KHR_vg_parent_image EGL_IMG_cl_image EGL_KHR_fence_sync
               EGL_IMG_context_priority EGL_IMG_hibernate_process
               EGL_IMG_image_plane_attribs EGL_KHR_surfaceless_context
               EGL_KHR_wait_sync EGL_KHR_create_context
               EGL_WL_bind_wayland_display EGL_EXT_image_dma_buf_import
[09:22:46.712] GL version: OpenGL ES 2.0 build 1.14@3699939 (MAIN)
[09:22:46.712] GLSL version: OpenGL ES GLSL ES 1.00 build 1.14@3699939 (MAIN)
[09:22:46.712] GL vendor: Imagination Technologies
[09:22:46.712] GL renderer: PowerVR SGX 544MP
[09:22:46.712] GL extensions: GL_OES_rgb8_rgba8 GL_OES_depth24
               GL_OES_vertex_half_float GL_OES_texture_float
               GL_OES_texture_half_float GL_OES_element_index_uint
               GL_OES_mapbuffer GL_OES_fragment_precision_high
               GL_OES_compressed_ETC1_RGB8_texture GL_OES_EGL_image
               GL_OES_EGL_image_external GL_OES_required_internalformat
               GL_OES_depth_texture GL_OES_get_program_binary
               GL_OES_packed_depth_stencil GL_OES_standard_derivatives
               GL_OES_vertex_array_object GL_OES_egl_sync GL_OES_texture_npot
               GL_OES_surfaceless_context GL_EXT_discard_framebuffer
               GL_EXT_blend_minmax GL_EXT_multi_draw_arrays
               GL_EXT_multisampled_render_to_texture GL_EXT_shader_texture_lod
               GL_EXT_texture_format_BGRA8888 GL_EXT_occlusion_query_boolean
               GL_EXT_texture_rg GL_EXT_draw_buffers
               GL_EXT_shader_framebuffer_fetch GL_IMG_shader_binary
               GL_IMG_texture_compression_pvrtc
               GL_IMG_texture_compression_pvrtc2 GL_IMG_texture_npot
               GL_IMG_texture_format_BGRA8888 GL_IMG_read_format
               GL_IMG_program_binary GL_IMG_uniform_buffer_object
               GL_IMG_multisampled_render_to_texture GL_KHR_debug
[09:22:46.712] GL ES 2 renderer features:
               read-back format: RGBA
               wl_shm sub-image to texture: no
               EGL Wayland extension: yes
[09:22:46.712] Chosen EGL config details:
               RGBA bits: 8 8 8 8
               swap interval range: 1 - 1
[09:22:46.712] cursor buffers unavailable, using gl cursors
[09:22:46.712] Failed to initialize backlight
[09:22:46.712] Output Virtual-1, (connector 24, crtc 26)
               mode 1280x720@60.0, preferred, current
[09:22:46.713] Compositor capabilities:
               arbitrary surface rotation: yes
               screen capture uses y-flip: yes
               presentation clock: CLOCK_MONOTONIC, id 1
[09:22:46.714] Loading module '/usr/lib/weston/desktop-shell.so'
[09:22:46.717] launching '/usr/libexec/weston-desktop-shell'
[09:22:46.858] Warning: computed repaint delay is insane: -8879 msec
[09:25:43.272] queueing pageflip failed: Invalid argument
[09:25:46.887] unexpectedly large timestamp jump (from 185290 to 188905)

Part Number:TDA2EVM5777

Tool/software: Linux

Hi, 

My chain is consists of
--------------------------------------------------------------------------------------------------- 

NullSource(A15) (ch0~3) -> Merge_cap(A15) -> Decode -> VPE_cap ->
Dup_cap -> Sync_cap -> SgxFrmcpy(A15) -> Display

Dup_cap -> Select

Select -> VPE_dl -> Dup_dl

Dup_dl -> Merge_dl

Dup_dl -> Alg_tidlpreproc (DSP1)

Alg_tidlpreproc (DSP1) -> Alg_tidl_Eve1 (EVE1)
Alg_tidlpreproc (DSP1) -> Alg_tidl_Eve2 (EVE2)
Alg_tidlpreproc (DSP1) -> Alg_tidl_Eve3 (EVE3)
Alg_tidlpreproc (DSP1) -> Alg_tidl_Eve4 (EVE4)

Alg_tidl_Eve1 (EVE1) -> Merge_OD(DSP1)
Alg_tidl_Eve2 (EVE2) -> Merge_OD(DSP1)
Alg_tidl_Eve3 (EVE3) -> Merge_OD(DSP1)
Alg_tidl_Eve4 (EVE4) -> Merge_OD(DSP1)
Merge_OD(DSP1) -> Alg_tidl_Dsp (DSP1) -> Merge_dl

Merge_dl -> Sync_dl -> Alg_tiop(DSP1) -> Null(A15)

--------------------------------------------------------------------------------------------------- 

The Sgx side is working normally but the VPE link of TIDL side (that is after Select link) is not receiving any frames from Select link.

When i print each link statistics, the links in TIDL side didn't show any input & output FPS.

I changed the ProcessData func in Select link link below.

--------------------------------------------------------------------------------------------------- 

if (inBufList.numBuf)
{
Vps_printf("SELECT : inBufList numBuf %d", inBufList.numBuf);
for (bufId = 0; bufId < inBufList.numBuf; bufId++)
{
#if 1
pBuf = inBufList.buffers[bufId];

UTILS_assert(pBuf->chNum < SYSTEM_MAX_CH_PER_OUT_QUE);

pChInfo = &pObj->inChInfo[pBuf->chNum];

pSysCompBuf = (System_VideoFrameCompositeBuffer *)pBuf->payload;

for (frameId = 0; frameId < pSysCompBuf->numFrames; frameId++)
{
for (planeId = 0; planeId < SYSTEM_MAX_PLANES; planeId++)
{
pVidBuf->bufAddr[planeId] = pSysCompBuf->bufAddr[planeId][frameId];
}
pVidBuf->metaBufSize = pSysCompBuf->metaBufSize;
pVidBuf->metaFillLength = pSysCompBuf->metaFillLength;
pVidBuf->chInfo = pSysCompBuf->chInfo;
pVidBuf->flags = pSysCompBuf->flags;
}

pOutBuf->payload = pVidBuf;
pOutBuf->bufType = SYSTEM_BUFFER_TYPE_VIDEO_FRAME;
pOutBuf->payloadSize = sizeof(System_VideoFrameBuffer);
pOutBuf->chNum = 1;

UTILS_assert(pOutBuf != NULL);

#else

--------------------------------------------------------------------------------------------------- 

Could you please let me know whether there is any incorrect things in that?

Thanks & Regards,

YOO

Part Number:AM5718

Hi All,

In my schematic of AM5718 based board, the RGMII0_TXD[3:0] pins are connected in reverse with TXD0 connected as MSB and TXD3 as LSB as shown in the figure.

Is is possible for the software to do the swapping to nullify the issue? Please suggest some workaround

Thanks and Regards,

Rajneesh

Part Number:TDA2PXEVM

Tool/software: TI-RTOS

The problem I mentioned in the previous post has not been resolved, so I have to re-release it. I am using TDA2Px EVM, TDA2px Null Source (SD/Network) Input + Radar FFT (EVE1) + Null (SD/Network). According to the suggestion of the previous post, the network port can be successfully pinged, but I can't get the user guide. The output file mentioned and the heat map displayed by the LCD, whether you choose TCP/IP or TFDFTP, SDCard, will get an error: [DSP1] 177.605288 s: UTILS: MBX: Utils_mbxSendCmd(): Msg Alloc Failed (0)!!!

https://e2e.ti.com/support/processors/f/791/p/816419/3021518#3021518        

This is the post I posted last time. No one answered the question I mentioned later. I hope someone can help me solve this problem. thank you very much.

Part Number:TMDSICE3359

Hi guys,

a customer wants to implement AM3356 with PMIC TPS65910 and DDR3-RAM by Micron like in TMDSICE3359. Instead of using the DDR3-RAM version specified for 0°C (supply voltage 1.5V) they want to use the -40°C (supply voltage 1.35V) version.

According to the datasheet the PMIC can only supply down to 1.5V on VIO SMPS. To get the needed 1.35V an idea would be to switch VIO SMPS with VDD2 SMPS. For that the boot sequence would probably need to be altered. Is this possible or can you recommend an alternative solution e.g. another PMIC?

Thank you,

Franz

Part Number:AM5728

Tool/software: Linux

Hello,

I need GPIO access for one PRU of the AM572x (Beagleboard X15). I'm using PROCESSOR-SDK-LINUX-RT-AM57X  05_03_00_07.

I used the Pinmux Tool to add the PRU GPI/GPO and the Pearl script to create the output for editing U-Boot. After that I edited the existing lines and added non-existing lines in mux_data.h (iodelay.txt to iodelay_cfg_array_x15_sr2_0[] and iopad.txt to core_padconf_array_essential_x15[]) .

I then recompiled U-Boot and copied the new MLO and u-boot.img to the boot partition.

I also added the content of devicetree.txt:

&dra7_pmx_core {

};

&dra7_iodelay_core {
// for linux kernel 4.4 / processor sdk 3.x
};

to am57xx-beagle-x15-revc.dts and recompiled linux-dtbs, but I think that does not effect anything. I then renamed the dtb to am57xx-beagle-x15-revc-new.dtb and added a line fdtfile=am57xx-beagle-x15-revc-new.dtb to uEnv.txt to be sure it is used (and it seems to work).

I booted Linux to let u-boot make the pinmux config and used the XDS110 and CCS to run a simple assembly programm on PR1_PRU0 to set and reset R30 for testing the pins. But I don't see any changes on the GPOs after writing to R30.

I think there is something wrong with my pinmux configuration. For my programm I assume that pin pr_1_pru0_gpo1 is position 1 << 1 in R30. 

Is there any point that I am missing?

I attached the Pinmux project and the created files.

(Please visit the site to view this file)

Part Number:AM5728

Tool/software: Code Composer Studio

Hello,

I completed the EMIF tools spreedsheet with data corresponding to my custom board and it generate a gel function after saving the user config.

it notify that we can copy paste the text into the Gel source file. I'm not really sure the gel file it ask for. The only gel lfile that make sense to modify is "AM572x_ddr_config.gel"

I added the function and I modify the location where the original function was called in order to call the new function instead.

When I launch the script "AM572x_DDR3_532MHz_Config" I don't see any change.. (normal is just registers update) but at the and of the script, the printf write (2GB total)"

Actually, my board has a total of 4GBytes DDR3 (2x 512Mx16 on EMIF1 and 2x 512Mx16 on EMIF2).

I dont know how/where to specify this change into the gel file (I guess that it's not just a printf to modify :) )

Any help would be great.

Regard,

Sylvain.

Part Number:AM3354

Tool/software: Linux

Hi,

I am rebuilding the latest 5.03 PSDK Linux and encountering the error as in the attached log. The /home/root1/michael/tisdk/build/arago-tmp-external-linaro-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-tidl-import/01.01.00.00-r0/recipe-sysroot-native/usr/lib  buffer seem to contain both protoc and protobuf libraries.  

Any idea what could be wrong here?

thanks

Michael

(Please visit the site to view this file)

Part Number:AM5716

Tool/software: Linux

I have a custom AM5716-based board with 2 parallel NOR flash chips and trying to make them work in Linux as physical memory mapped MTD devices. It works in U-Boot, and does not work in Linux.

.config: enabled CONFIG_MTD_PHYSMAP, CONFIG_MTD_PHYSMAP_OF

device tree (partial):

#include "dra7.dtsi"

&gpmc {
        status = "okay";
        u-boot,dm-spl;

        #address-cells = <2>;
        #size-cells = <1>;
        ranges = <0 0 0x08000000 0x02000000>,   /* CS0: NOR 32M */
                 <1 0 0x0a000000 0x02000000>;   /* CS1: NOR 32M */

        nor@0,0 {
                compatible = "issi,is29gl256", "cfi-flash";
                reg = <0 0x00000000 0x02000000>;

                // Generic bindings
                linux,mtd-name = "issi,is29gl256";
                bank-width = <2>;
.....

 Kernel boot log (with added extra printk):

[    0.426220] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    0.426230] gpmc_mem_init: cs=0
[    0.426239] gpmc_mem_init: cs=0, base=00000000, size=01000000
[    0.426253] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    0.426261] gpmc_mem_init: cs=1
[    0.426268] gpmc_mem_init: cs=2
[    0.426275] gpmc_mem_init: cs=3
[    0.426281] gpmc_mem_init: cs=4
[    0.426288] gpmc_mem_init: cs=5
[    0.426294] gpmc_mem_init: cs=6
[    0.426301] gpmc_mem_init: cs=7
[    0.426307] gpmc_probe: gpmc_mem_init called
[    0.426647] gpmc_probe: gpmc_gpio_init ok
[    0.426910] gpmc_probe: gpmc_setup_irq ok
[    0.426921] gpmc_probe_generic_child
[    0.426950] gpmc_probe_generic_child name=(null) cs=0 res=[mem 0x08000000-0x09ffffff]
[    0.426966] gpmc_cs_set_memconf: cs=0 base=02000000 size=02000000
[    0.426975] gpmc_probe_generic_child gpmc_cs_request ret=0
[    0.427036] gpmc_probe_generic_child gpmc_cs_disable_mem(cs=0) called
[    0.427054] gpmc_cs_set_memconf: cs=0 base=08000000 size=02000000
[    0.427062] gpmc_probe_generic_child gpmc_cs_remap ret=0
[    0.427072] gpmc_probe_generic_child bank-width = 2
[    0.427080] gpmc_probe_generic_child gpmc_cs_program_settings cs=0 ret=0
[    0.427102] gpmc_probe_generic_child gpmc_cs_set_timings cs=0 ret=0
[    0.427109] gpmc_probe_generic_child gpmc_cs_enable_mem called
[    0.427320] gpmc_probe_generic_child
[    0.427346] gpmc_probe_generic_child name=(null) cs=1 res=[mem 0x0a000000-0x0bffffff]
[    0.427361] gpmc_cs_set_memconf: cs=1 base=02000000 size=02000000
[    0.427370] gpmc_probe_generic_child gpmc_cs_request ret=0
[    0.427428] gpmc_probe_generic_child gpmc_cs_disable_mem(cs=1) called
[    0.427445] gpmc_cs_set_memconf: cs=1 base=0a000000 size=02000000
[    0.427452] gpmc_probe_generic_child gpmc_cs_remap ret=0
[    0.427461] gpmc_probe_generic_child bank-width = 2
[    0.427469] gpmc_probe_generic_child gpmc_cs_program_settings cs=1 ret=0
[    0.427491] gpmc_probe_generic_child gpmc_cs_set_timings cs=1 ret=0
[    0.427498] gpmc_probe_generic_child gpmc_cs_enable_mem called
[    0.427696] gpmc_probe: gpmc_probe_dt_children called
[

It looks like CS0 and CS1 are mapped to proper memory ranges, but in reality neither CFI probe works, nor busybox devmem 08000000 returns real data. Seems like memory is not mapped in Linux.

The line 'gpmc_cs_set_memconf: cs=0 base=02000000 size=02000000' seems to be wrong, but there is a comment in the omap-gpmc.c which explains this as normal, since the start address later is remapped to the proper value:

        /*
         * FIXME: gpmc_cs_request() will map the CS to an arbitary
         * location in the gpmc address space. When booting with
         * device-tree we want the NOR flash to be mapped to the
         * location specified in the device-tree blob. So remap the
         * CS to this location. Once DT migration is complete should
         * just make gpmc_cs_request() map a specific address.
         */
 

The problem is that AM57xx IDK kits do not have parallel NOR flash, so no known good config is available. From the other side, this mapping works in U-boot. I verified this with both md, cp commands and also stopping U-Boot in Code Composer Studio and checking flash from memory browser. Even CFI flash probe works from CCS (by writing 0x0098 to address 080000AA and reading CFI tables from corresponding addresses). So I definitely sure that the hardware works.

What else could be wrong with this Linux setup? The device tree is custom-made, it includes dra7.dtsi, and then enables gpmc as shown above.

Part Number:TMS320C5535

Hi,

I see that 5535 is in NRND (not recommended for new design) category. So how long is it going to remain in production before getting obsolete ? 6 months? 1 yr?

Regards,

Dileepan.

Part Number:AMIC110

Hi Sir 

    if as the EtherCAT to make IO control.The Chip AMIC110 wether not use the  external DDR? And Have some training or user  document to help me complete a example project?

Part Number: TDA2P

Tool/software: TI-RTOS

Hi All,

We have D0-D15 ,Hsync, Field and Pix clock connected to LCD3 interface of TDA2PX.

I need RGB565 Interlaced output. I tried changing the scan format in chains_common.c  from SYSTEM_SF_PROGRESSIVE to SYSTEM_SF_INTERLACED.

I am getting Assertion from DSS

[IPU1-0] 9.724455 s: DISPLAY: Create in progress !!!
[IPU1-0] 9.724760 s: dispcore/src/vpscore_dss.c @ Line 1412:
[IPU1-0] 9.724852 s: Format(interlaced/progressive) conversion is not supported
[IPU1-0] 9.724943 s: dispdrv/src/vpsdrv_displayCore.c @ Line 304:
[IPU1-0] 9.725065 s: Set DSS parameter failed

Does LCD interface does not support Interlaced data?

Is there any way to output RGB 565 interlaced data from SoC

Currently I am using VSDK 3.05 version.

Regards,

Deepika

Part Number:TDA2EXEVM

Hi,

There's a problem，I use the ssdJacintoNetV2 which is Ti provided Object detect net.

In the identification of traffic signs, one kind of images often make mistakes, resulting in low identification errors.

just show as blow. The left image is belong to the speed limit signs, which I need to recognize in my task, but the right image is very similar to the left，which not in my task. How can I strengthen my training for this situation？The right image is not marked in my sample.

1、Can I use subclass attributes to reinforce the training of the sample?

2、We want to get a good result of vehicle identification at night，For ssdJacintoNetV2 networks, I need to separate night vehicles into another one category or a subcategory，or just in the car category without subdivision？

typedef struct
{
uint32_t objTag;
uint32_t objType;
uint32_t objSubType;
uint32_t xPos;
uint32_t yPos;
uint32_t objWidth;
uint32_t objHeight;
float    objScore;
float    objScale;
float    reserved0;
float    reserved1;
float    reserved2;
} TI_OD_objectDescriptor;

Part Number:PROCESSOR-SDK-AM335X

Tool/software: Linux

Hi,

I am using beaglebone black. It has already loaded with OS in eMMC, and it is booting from there.

I tried the step for switching boot process from eMMC to uSD card from this .

But Second LED is failed to blink.

How can I boot from SD card.

Is there any other way.

Thanks and regards,

Vishnu

Part Number:AM5749

Tool/software: Linux

I want to know if I set the inputdata's batchsize = 2,  Does the EVE compute two input graphs at the same time or does it cycle through them twice?

input_shape {
  dim: 2
  dim: 1
  dim: 32
  dim: 32
}

I have two channels of camera image input, hoping to keep the computation synchronized。

Part Number:OMAP-L138

Tool/software: Linux

The latest TI BSP for OMAP-L138 is 05_03_00_07 which supports kernel version 4.14.  Does this new BSP work with DSPLink ?  Is there a need to upgrade to SysLink ?

hi, i am new to TI 

we are trying to build a protocol gateway (MODBUS and OPC-UA are main) where we need to collect the variables (around 20 thousand of quantity in total from both Ethernet and RS-485 combined) from MODBUS and CAN, then process those variable using multiple mathematical operations then we need to send it into a OPC UA client. this is the main purpose. now on top of this base program i want a local Webserver and RTOS (any soft-RTOS) to run. display and analogue input are least of my requirements, i want a high performance processor than can work upto 4 to 70 degree Celsius without any issue. high power consumption is not a problem as long as thermal handling is simple. 

basically the product will be a communication gateway with few Digital inputs and outputs to filed devices ( a Programable Logic Controller in base). any help in selecting the processor is much appreciated.

i was looking into this "am5k2e04" and it looks good enough for me, please let me know your  thoughts. thanks