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PROCESSOR-SDK-AM335X: Compilation error

June 5, 2019, 10:32 pm
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Part Number:PROCESSOR-SDK-AM335X

Hi,

I created a project for turning on LED according to Processor RTOS Getting Started Guide Section 6.5 GPIO, but it is showing some error. I am attaching a JPEG File. Please suggest any solution.

Regards

Gaurav

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Unable to get MSI Interupt generated at RP.

June 5, 2019, 11:03 pm
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I'm a part of post silicon validation. I'm trying to generate an MSI Interrupt at RP, but could not do so.

I have EP PCIe card connected to RP.

1. Enabled BME and Memory space at both EP and RP.

2. Enabled MSI at both EP & RP.

3. Current MSI address at EP is 0x0

4. Current MSI Data at EP - 0x0

5. Current MSI address at RP is 0x3fb83c03

6. Current MSI Data at RP is 0x41c

I'm not understanding how to configure MSI address (based upon current RP address?)

And how to check if actually MSI Interrupt generated or not?

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TDA2EVM5777: TIDL issues with Tensorflow 1.1 networks import

June 5, 2019, 11:24 pm
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Part Number:TDA2EVM5777

hello everybody , 

please  During conversion of several networks from Tensorflow 1.10 to TIDL format, using the import tool, these issues were found:

  • Op Type Shape is Not suported
  • Op Type StridedSlice
  • Op Type Pack
  • Op Type Conv2DBackpropInput
  • Op Type Maximum

could you help ?  where can I find details on TIDL limitations ?

thank you 

best regards

Carlo

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TDA2EVM5777: how to modify input file for TDA2 evm on SDcard

June 5, 2019, 11:32 pm
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Part Number:TDA2EVM5777

Hi everybody , 

please about the input video file to be placed together with the final files on the SD card of the board. The video provided from TI  ( inputdata ) , that is also used in the segmatic demo, is in a binary format and it is  not possible to convert it to a standard video  file.

I  would like to know how to change the input video , and how to create it froma a standard video format .

best regards

Carlo

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Linux/TMDSICE3359: Boot time optimization

June 5, 2019, 11:35 pm
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Part Number:TMDSICE3359

Tool/software: Linux

sdk 5.01

Linux RT arago.

AM3359 Industrial Communications Engine (ICE)

Hi!
I have to minimize the time of boot of ICE.

So, I have remove the sevices, by "systemctl disable [service]" and by remove the links from rcX.d.
Result: the boot time has no changed.

Am I have to setup the uboot? By changing the dts-files?

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Importing onnx model through Import tool

June 5, 2019, 11:35 pm
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Dear Sir,

I converted the Tensorflow model to onnx model, now i want to import the same converted model through TIDL Import tool to generate .bin files.

I have gone through TIDL Deep Learning user guide, but  I couldn't find any reference for this process other then Tensorflow and Caffe models.

Kindly help me in this.

Thanks and Regards,

Shivansh Agnihotri

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RTOS/AM5728: I2C R/W inconsistency

June 5, 2019, 11:35 pm
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Part Number:AM5728

Tool/software: TI-RTOS

Hi,

this is the follow up question to the problem mentioned in the link below

we were able to address the problem by doing the code download from the ARM(linux) because it was very consistently taking around 4 sec for doing the same download but the DSP still has to communicate with the same slave device using I2C read,write which can't be done from ARM. This was achieved by the ARM side first doing the code download and sending a message to the DSP notifying the same. Upon receiving the this message, we pinmux the I2C bus from the DSP(given below) and carryout some periodic I2C transactions by pinmuxing the bus opening the bus performing read/write and closing the bus on each transaction. (Note: The ARM doesn't do any transactions after this to avoid conflict over the bus)

(PINMUX from DSP)

regVal = 0x60002;
((CSL_padRegsOvly)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPIO6_10 = regVal;

regVal = 0x60002;
((CSL_padRegsOvly)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPIO6_11 = regVal;

CSL_l4per_cm_core_componentRegs *l4PerCmReg =
(CSL_l4per_cm_core_componentRegs *) CSL_MPU_L4PER_CM_CORE_REGS;

CSL_FINST(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST));

It is observed that the I2C read and writes are not consistent. We saw that 10 out of 100 write  resulted in it failing almost 10-20 times with I2C_STS_ERR_TIMEOUT and the read are even worse with almost 10-30 read fails with I2C_STS_ERR_TIMEOUT.

We then tried to debug it by doing the some read transactions and capturing it using a logic analyzer to see what was going wrong and following was observed,

  • Code download from  DSP  and read from  DSP  it  was seen that the delay between the write and read frame varies from 50-600 us.  No fails seen out of 1000 reads.

  • Code download from ARM and read from ARM it  was seen that the delay between the write and read frame is around 40-60 us every time. No fails seen out of 1000 reads.

  • Code download from ARM and read from  DSP it  was seen that the delay between the write and read frame  varies from 5-600 us, at times whenever read took <20us we saw that the read failed with the clock stretching untill timeout.

we noticed a peculiar observation from the captures, was that there is no clock stretching  just after the address read block from ARM but it does stretch every time from DSP.

Conclusion

  • If we were to perform the read from the same core where the code download happened the read never failed.
  • When the i2c peripheral is shared i.e., we were to perform the read from the  DSP core and the code download form  ARM read becomes inconsistent and fails.

ideally the code download and read/write transactions should happen in the DSP but as mentioned in the link above we are not able to do it because the timing is inconsistent taken to download from DSP and hence download was moved to ARM and read write transactions done from DSP because it required do so.

I2c driver configurations from DSP ad follows,

bus_no = 2;

i2c_cfg.enableIntr = true;

I2C_socGetInitCfg(bus_no, &i2c_cfg);



I2C_socSetInitCfg(bus_no, &i2c_cfg);

/*
* AM5 DSP does not have a default Xbar connection for I2C
* interrupt, need the following Xbar interrupt configuration
*/
/* Use reserved DSP1_IRQ_86 for I2C bus 5 */
CSL_xbarDspIrqConfigure(DSP_INSTANCE, CSL_XBAR_INST_DSP1_IRQ_86, CSL_XBAR_I2C5_IRQ);

/* Use reserved DSP1_IRQ_87 for I2C bus 3 */
CSL_xbarDspIrqConfigure(DSP_INSTANCE, CSL_XBAR_INST_DSP1_IRQ_87, CSL_XBAR_I2C3_IRQ);
I2C_init();

I2C_Params_init(&i2cParams);
i2cParams.bitRate = I2C_400kHz;

i2c_bus_handle_st[bus_no].i2c_handle = I2C_open(bus_no, &i2cParams);

we are using ti provided I2C_Transfer to read/write from DSP and ioctl for I2C transfer from ARM.

bios version: 6_52_00_12

pdk ver: pdk_am57xx_1_0_7

IPC version: 3_47_00_00

Thanks 

Ranganath

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TDA2EVM5777: TIDL learning lib issue in building , how to use vcvarsall.bat

June 5, 2019, 11:37 pm
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Part Number:TDA2EVM5777

Hi everybody ,

problem was found during the Building of source on host emulation(section 3.5 of TiDeepLearningLibrary_UserGuide.pdf )

Unclear instructions on how to use vcvarsall.bat (section 3.5.2 of TiDeepLearningLibrary_UserGuide.pdf) .

could you kindly give  proper options  to the bat file  to use to do right  instruction ?

beste regrads

Carlo

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TMDSICE3359: ICEv2 factory settings

June 5, 2019, 11:41 pm
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Part Number:TMDSICE3359

Hello, I 've few question :

-What is the Kernel of AM3359? (Is it a Linux RT, Linux or TI-RTOS kernel?)

-And what is the pre installed Operating System on this processor?

-And I need to change the OS of this processor if we use the Processor SDK Linux RT, the Processor SDK Linux or the Processor SDK RTOS?

Thanks.

Best regards,

Florian

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TDA2EVM5777: issues in rebuilding TIDL import tool both using command and bash file

June 5, 2019, 11:45 pm
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Part Number:TDA2EVM5777

Hi everybody , 

In this page : https://e2e.ti.com/support/processors/f/791/t/689876 is mentioned that by updating the "tidl_tfImport.cpp" and re-building the import tool in the release package we can modify or add layers.   We tried to rebuild the import tool as described in the TIDeepLearningLibrary_UserGuide.pdf (section 3.6.1).

I get errore both on command and on bash(Please visit the site to view this file) ( see screenshot attached )  .How can I proceed  ?

I m on WIN10 64 bits 

best regrads

Carlo

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RTOS/AM5728: sys_nirqx function for SMP

June 6, 2019, 12:33 am
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Part Number:AM5728

Tool/software: TI-RTOS

Hello, TI Experts,

 

Our customer sent us additional questions about sys_nirqx function of AM5728 from the below E2E thread.

https://e2e.ti.com/support/processors/f/791/p/779630/2885183#2885183

 

They can create their program to use sys_nirq1 and sys_nirq2 on A15_0 like below statements.

Thank you !

>hndHwiIrq1 = Hwi_create(39, intProcIrq1, NULL, NULL);

>hndHwiIrq2 = Hwi_create(151, intProcIrq2, NULL, NULL);

 

 

They tied to improve their program by using SMP function with A15_0 & A15_1.

And they said they can also success to run sys_nirq1 and sys_nirq2 function

with only *.cfg fie modification like below;

- BIOS.smpEnabled = true;

 

Question:

- Are thee any problem by using NULL parameter like below?

  >hndHwiIrq1 = Hwi_create(39, intProcIrq1, NULL, NULL);

  >hndHwiIrq2 = Hwi_create(151, intProcIrq2, NULL, NULL);

- Are there any additional code modification by using sys_nirq1 and sys_nirq2 function with SMP?

- Could you tell us the recommended way or sample code by using sys_nirq1 and sys_nirq2 function with SMP?

Best regards,

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RTOS/66AK2G12: USB FIFO configurations

June 6, 2019, 12:47 am
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Part Number:66AK2G12

Tool/software: TI-RTOS

Hello,

My customer would like to confirm the USB FIFO configuration in PDK implementation.

Please take a look at C:\ti\pdk_k2g_<latest version>\packages\ti\drv\usb\src\dwc\usb_dwc_dcd.c

void usbDwcDcdSetConfiguration(usbDwcDcdDevice_t *dwc3)
{
    uint32_t bulkInFifoSize, ep0CtrlMps, epBulkMps;
    volatile uint32_t regVal;

    tDeviceInfo*        ptDeviceInfo;

    /* This has to be done based on the speed */
    /* Check this logic */
    bulkInFifoSize = ((2U * (1024U + 8U) + 8U) / 8U);
    ep0CtrlMps = 64U;
    epBulkMps = 512U;

Here, it seems like the FIFO size hard-corded by ((2U * (1024U + 8U) + 8U) / 8U). And bulkInFifoSize will be used to configure USB related registers.

    regVal = HW_RD_REG32(dwc3->baseAddr + DWC_USB_GTXFIFOSIZ1);
    HW_SET_FIELD(regVal, DWC_USB_GTXFIFOSIZ0_TXFSTADDR, 66U);
    HW_SET_FIELD(regVal, DWC_USB_GTXFIFOSIZ0_TXFDEP, bulkInFifoSize);
    HW_WR_REG32(dwc3->baseAddr + DWC_USB_GTXFIFOSIZ1, regVal);

    regVal = HW_RD_REG32(dwc3->baseAddr + DWC_USB_GTXFIFOSIZ2);
    HW_SET_FIELD(regVal, DWC_USB_GTXFIFOSIZ0_TXFSTADDR, 66U + 256U);
    HW_SET_FIELD(regVal, DWC_USB_GTXFIFOSIZ0_TXFDEP, bulkInFifoSize);
    HW_WR_REG32(dwc3->baseAddr + DWC_USB_GTXFIFOSIZ2, regVal);

Considering the macro definitions, these registers would be :

  • 0x0269C304U and 0x0269C308U for USB0
  • 0x0259C304U and 0x0259C308U for USB1

I don`t know whether these are TI specific registers or USB IP Core registers. Can you comment ?

Some background:

They had a trouble with USB Audio and MSC composite operation with their USB driver code, which is based on TI PDK example. The driver worked basically, but sometimes, something error raised in runtime. And if they changed the FIFO size configuration (bulkInFifoSize in TI driver code), it seemed the error did not happen. So they want to know the reason for that.

As you see in the original post, I understand that there is no USB related information in TRM. And we need NDA with USB IP vendor for further information. As for TI wrapper registers, I understand these should be exactly same configuration with TI examples (Ex. PDK or Linux driver implementation). Unfortunately, my customer does not have NDA for now. They are finding right parson to have NDA with IP vendor to get the IP document and understand why the error does not happen by changing the above registers. But, you know, these registers might be TI related registers. So I`m asking if the above registers are TI part or IP vendor part.

Best Regards,
NK

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66AK2G12: GPMC Questions

June 6, 2019, 1:12 am
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Part Number:66AK2G12

Dear All,

we have a custom board with an 66AK2G12 where we interface some chips via GPMC.

The PDK I am using is "pdk_k2g_1_0_13" from the latest SDK "processor_sdk_rtos_k2g_5_03_00_07"
The TRM I am referring to is "SPRUHY8I January 2016–Revised March 2019"

After searching for details I am left with some open points to clarify:

  • For a NOR flash with non-multiplexed data and address lines, is the addressable space really limited to 2KB in size?
    In the forums I found that for some other devices this statement is only wrong in the TRM but not true for the chip.
    Please can you tell me what is correct?

  • In the example code located at "pdk_k2g_1_0_13\packages\ti\board\diag\nand\src" there is a call "GPMCLimitedAddrDevSupportConfig"
    But the affected bit 1 in the GPMC config register is defined as "reserved" in the TRM
    Please tell me if it is relevant to clear the bit to not have the 2KB address limitation

  • I have problems to understand the address decoding
    We have a CPLD connected to A1-A3 D0-D7 on CS1 so what is the physical address to be used?
    There are 8 valid addresses 0x00000000-0x0000000E
    Are these settings for GPMC_CONFIG7 correct? base: 0b000000, mask: 0b1111 (16MB)
    So this reserves address range 0x00000000-0x01000000 for CS1 and only 8 addresses are used

  • What is the address I have to use in my code? The GPMC_0_DATA is located at 0x30000000-0x3fffffff from memory map.
    So will the cs1 address range be 0x30000000-0x31000000?
    For example to access the first two bytes i can use:
    volatile uint8_t* byte1_ptr = (volatile uint8_t*)0x30000000
    volatile uint8_t* byte2_ptr = (volatile uint8_t*)0x30000002
    Is this correct?

Looking forward to any reply,

Regards
Bernhard

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AM5716: Recommended Ethernet PHY

June 6, 2019, 2:18 am
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Part Number:AM5716

Hi Experts,

A customer has been looking for our recommended Ether Phy with AM5716.
They are considering two devices below:

1)DP83867　　10/100/1000 BASE-T

2)DP83822　　10/100 BASE-TX

Thank you very much for your kind check.
Best regards,
HItoshi



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Compiler/66AK2E05: GCC 7.2.1 unsupported behavior for C struct designated initializers

June 6, 2019, 2:44 am
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Part Number:66AK2E05

Tool/software: TI C/C++ Compiler

Hi ,

during compilation of one c file I get following error:

"sorry, unimplemented: non-trivial designated initializers not supported"

Compiler used is gcc (the one included by arago proj.) :

/home/<MyUsername>/ti-processor-sdk-linux-k2e-evm-05.03.00.07/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/arm-linux-gnueabihf-gcc --version
arm-linux-gnueabihf-gcc (Linaro GCC 7.2-2017.11) 7.2.1 20171011
Copyright (C) 2017 Free Software Foundation, Inc.

I have done search on my own and according to this post:  link

this is a known 'bug' or unimplemented behavior of GCC even though designated aggregator initializers are not a new feature, they rather belong to C99.

Do you know when ti (or arago linux first) will include GCC version 8 on their tool chain?

If it is coming some time soon I'd rather wait or else I may change my code totally ...

Thank you,

Br,

George

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What assembly instructions does '0x4704(in TI file)' correspond to?

June 6, 2019, 3:07 am
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I use CCS to create a Dsp.TI file.   In TI  file  for C54x chip, I found 0xF495   correspond to     asm("    nop");

What assembly instructions does '0x4704(in TI file)'  correspond to?

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AM5728: Make the camera connected via USB default as built-in camera not working in Android

June 6, 2019, 3:56 am
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Part Number:AM5728

Hello experts.

I have a AM572x Evaluation Module TMDSEVM572X with me and I have successfully compiled Android SDK 5.03 on it.

As per this thread, (posted by me), TI experts have made it clear that camera support is not provided with Android OS on this EVM. However, the USB camera works completely fine when attached to the EVM and is verified using a simple usb cam application. While, on the other hands, the system camera is not being detected at all.

Therefore, I would like to customize Android at a source level and add code to automatically switch the default (built-in/system) camera to the one connected by USB when it is available. Or if switching dynamically is not possible then disable the system camera and make USB (external) camera as the default one.

This way all applications should detect the external (USB) camera as the primary camera. For example, if I open camera application then the device should take the picture from the one which is connected via USB.

I have the Android SDK source code available with me, but I am not sure how to proceed.

Really appreciate your help.
Thanks!

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PROCESSOR-SDK-AM335X: Boot from NAND

June 6, 2019, 4:50 am
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Part Number:PROCESSOR-SDK-AM335X

Hi,

I need to load the application to nand flash memory and boot the processor from nand flash and the run the application. Could anyone tell me the procedure or details. 

Regards

Gaurav

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RTOS/PROCESSOR-SDK-DRA7X: Frame latency from Vsync Capture to Display Release is high when UC created from RTOS instead from HLOS

June 6, 2019, 4:57 am
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Part Number:PROCESSOR-SDK-DRA7X

Tool/software: TI-RTOS

(Please visit the site to view this file) has increased after starting use case from app/src/rtos/usecase.

Timestamps are taken at Capture Side (In Function CaptureLink_drvProcessData )  and  On Display Release side (DisplayLink_drvReleaseData).  

Note: Earlier we use to start the usecase from app/src/hlos/usecase, we use to max latency from Capture to display as 72ms now it is almost doubled.

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AM6548: The questions of DMA

June 6, 2019, 5:09 am
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Part Number:AM6548

Hi Team.

 

I have few questions of DMA.

How many transactions can be issued at same time?

How is Max Burst length?

 

Thanks and Best regards,

Kuerbis

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