Part Number:AM5728

Tool/software: TI-RTOS

Hi,

I am using  PROCESSOR-SDK-RTOS-AM57X - pdk_am57xx_1_0_7

we are trying to handle the interrupt which is triggered by the FPGA  to DSP on the gpio2_19 pin.

But, when we try to use this GPIO we receive bad IRQ interrupt in ARM linux.

Part Number:TDA2EVM5777

Tool/software: Linux

Dear experts,

We can find that HDMI input is supported when using bios_all with TDA2EVM+VisionBoard. But the similar usecase in VIsionSDK Linux doesn't work.

Is HDMI input supported in VisionSDK Linux? 

Thanks & Best Regards!

ZM

Part Number:AM3352

Tool/software: Linux

Hi,

  I used uart5 as 485 mode, but rts-gpio has no waveform output.

gpio2_0 used as rts-gpio

the dts file attached.uart5_pins: pinmux_uart5_pins {

pinctrl-single,pins = <
AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2[0] rs485 io-gpio */
AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE3) /* (H16) gmii1_col.uart5_rxd */
AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* (H18) rmii1_refclk.uart5_txd */
>;
};

&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins>;
status = "okay";
rts-gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
rs485-rts-active-high;
rs485-rts-delay = <1 1>;
linux,rs485-enabled-at-boot-time;
};

&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&gpio2_pins_default>;
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};

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Part Number:TDA2PXEVM

Tool/software: Linux

Hi,

I'm trying to implement image scaler using VPE. The parameters of VPE are following.

 - IN resolution: (2816 x 1080)
 - OUT resolution : (1920 x 1080) or (1920 x 1080*1920/2816)

There were errs  as below.

   Assertion @ Line: 438 in hal/src/vpshal_dei.c: config->width <= VPSHAL_DEI_MAX_DEI_WIDTH : failed !!!

Is it the limitation of VPS scaler?
In TRM, I could find only the limitation of output size. "Maximum horizontal scaling ratio only limited by output line buffer (2047 pixels) "

Regards,
HJ Kim

Part Number:AM3352

When program reached at line 199, that is to say, the program already executed line 198.

The F bit in CPSR will not be changed.

Part Number:TDA2EVM5777

Tool/software: Linux

Hello People,

I tried to setup the linux(ubuntu 14.04) based host system to build the VISION SDK , i am new to linux environment and the command line, i am following the document VISION SDK LINUX user guide.pdf from TI to setup the machine.

I am little confused over the following commands

2.4 section of user guide

export INSTALL_DIR=<installation_directory_absolute_path>

i got this is setting up the environmental variable  for the directory, my question is does this mean that i have to run it like following if my vision sdk is installed under

folder  /opt

export INSTALL_DIR=/opt/PROCESSOR_SDK_VISION_03_06_00_00?

 2.4.2.1.4 section

& how to setup following when image is untar inside the location $INSTALL_DIR/ti_components/os_tools/linux/targetfs

export INSTALL_DIR=<installation_directory_absolute_path>

I am getting the following error when i try to run the make linux command after setting up the Rules.make file for  MAKECONFIG?=tda2xx_evm_linux_all

root@lnmiit-HP-ProDesk-400-G2-MT:/opt/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/build# make linux
make -C ./hlos/makerules/linux -f build_uboot.mk uboot
make[1]: Entering directory `/opt/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/build/hlos/makerules/linux'
make -fbuild_uboot.mk uboot_build UBOOT_TARGET=dra7xx_evm_vision_config
make[2]: Entering directory `/opt/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/build/hlos/makerules/linux'
make -C /opt/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/../ti_components/os_tools/linux/u-boot/u-boot ARCH=arm CROSS_COMPILE=/opt/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/os_tools/linux/linaro/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf- dra7xx_evm_vision_config
make[3]: Entering directory `/opt/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/os_tools/linux/u-boot/u-boot'
make[3]: *** No rule to make target `dra7xx_evm_vision_config'.  Stop.
make[3]: Leaving directory `/opt/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/os_tools/linux/u-boot/u-boot'
make[2]: *** [uboot_build] Error 2
make[2]: Leaving directory `/opt/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/build/hlos/makerules/linux'
make[1]: *** [uboot] Error 2
make[1]: Leaving directory `/opt/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/build/hlos/makerules/linux'
make: *** [uboot] Error 2
root@lnmiit-HP-ProDesk-400-G2-MT:/opt/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/build#

beacuse of the error above i think it is because of the setting up the Environmental Variables

??

Regards

sajad

Part Number:AM3352

Tool/software: Linux

Now my linux platform setup with ti-processor-sdk-linux-am335x-evm-05.02.00.10-Linux-x86-Install.bin.

UART0 UART1,UART2 run in edma mode.Now need UART3 UART4,UART5 also run in edma mode.

The problems as below:

1,If I modify am33xx.dtsi and config UART3 UART4 UART5 the same as MMC including Edma function.Will I need modify omap-8250.c file that is the uart driver?If I need,How to modify it?

2,How will the function effect the linux system.

Thank you

Best regards

Part Number:AM3352

Tool/software: Linux

Hello,

1,Now the dts file about Dual ethernet as below:

&mac {
slaves = <2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac = <1>;
// active_slave = <1>;
status = "okay";
};

&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};

&cpsw_emac0 {
phy_id = <&davinci_mdio>, <4>;
phy-mode = "rgmii-txid";
// dual_emac_res_vlan=<0>;
};

&cpsw_emac1 {
phy_id = <&davinci_mdio>, <6>;
phy-mode = "rgmii-txid";
// dual_emac_res_vlan=<1>;
};

2,operate step case 1:
1, ifconfig eth0 192.168.1.12 netmask 255.255.255.0
2, ifconfig eth1 192.168.1.13 netmask 255.255.255.0
3,The host computer is 192.168.1.22
4,connect eth0 to the host computer.
5,From the Board ,ping 192.168.1.22,OK.
6,Switch the cable,connect eth1 to the host computer.
7,From the Board ,ping 192.168.1.22,Fail!

3,operate step case 2:
1, ifconfig eth0 192.168.1.12 netmask 255.255.255.0
2, ifconfig eth1 192.168.2.13 netmask 255.255.255.0
3,The host computer is 192.168.1.22 and 192.168.2.22 on the same NIC card.
4,connect eth0 to the host computer.
5,From the Board ,ping 192.168.1.22,OK.
6,Switch the cable,connect eth1 to the host computer.
7,From the Board ,ping 192.168.2.22,OK!

help me fix it.

Thanks a lot.

Best regards

Part Number:DRA756

I have run the linux in DRA756 ,but A15 there is not enough operational capability for Lidar data process. So I want know how to use the DRA756  DSP-core ,and is there any reference documen or code?

Part Number:PROCESSOR-SDK-AM335X

Tool/software: Linux

I'm using the AM335X-EVM and run the arago-base-tisdk-image-am335x-evm filesystem in the SDK. But it works well at the u-boot process, but when the kernal is ready and I need to input the login name, it begins to print [26~^[ on th screen. 

So I can only use the tty0 as terminal. Now I'm trying to cross compile the tslib on it. The ts_calibrate can run, when I touch the screen it can return the point but the graphic interface just show and disappear very fast.

I really don't know what is wrong, the driver problem or the hardware problem.

Part Number:AM5708

Hi:

How does the AM5708 use pr1_uart, has it been verified that pr1_uart is available?

Part Number:PROCESSOR-SDK-AM65X

Tool/software: Linux

Dear TI team,

we're getting kernel panics from the icssg_prueth kernel driver whenever we have more than one PRU ethernet interface with an active link (attached to the same switch).

I've attached the serial console output from one test run where we've been using the prebuilt Linux images that come with the processor SDK Linux for the AM65x version 05.02, but the same problem occurs when using a kernel that we've built ourselves with Yocto, or when using a custom kernel (based on the same branch and commit as the processor SDK kernel) on our custom hardware.

The problem only appears when we have more than one Ethernet interface attached. It could be anything from "right after boot" to "after a few minutes" with no obvious relation to what we're doing, i.e. at some point the system crashes even if we're not doing anything, but it also "survives" a flood ping for several minutes.

There is a known issue "LCPD-14189" in the release notes but that doesn't contain a whole lot of information. Is this the same issue we're seeing? Is there a workaround available or a fix planned?

Regards,

Dominic

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Part Number:AM5728

Tool/software: Linux

Hi, Sir,

My hardware design is referenced to the am572x_gp_evm_REV_A3a.dsn, and I use ti-processor-sdk-linux-am57xx-evm-05.01.00.11.

I can't find the dts file like am57xx-evm-reva3.dts, I don't know which dts file I can refer to?

Part Number:AM5718

Tool/software: Linux

Hiii

Can anyone let me know how to check the DDR speed (clock frequency) in AM5718 IDK ?

Is there any specific command ?

I am using ti PSDK Linux 05.01.00.11.

Thanks and Regards...

Arpita jena

Part Number:TDA2EVM5777

Tool/software: Linux

Hi,

This is just a Query.

How does the Chains & Link framework that comes with the Ti Vision SDK compare to the Open Vx standard.

Basically, as i understand, both support creating graphs for vision applications.

Does it internally use the OpenVx standard?

Also, does the chains and links internally use OpenCL in any way to run on different cores.

Thanks and Regards,

AAA

Part Number:AM6548

Tool/software: TI-RTOS

Hello Experts,

I have an issue when triggering a cyclic interrupt from PRU to R5F core.

The cycle time of this interrupt is 125µs (plus 2 PRU cycles).

Because the TIRTOS Clock interrupt runs with 1ms cycle time (per default using the dmtimer peripheral), the clock interrupt and my PRU->R5F interrupt drift slowly against each other.

So each raise condition occurs you can think of. I can see it on the oscilloscope using some GPIO of the AM65_IDK (TIMER_IO0/1 at J19).

The R5F VIM seem to support interrupt priorities from 0 (highest) to 15 (lowest):

• for my cyclic interrupt I use a TIRTOS HWI with the priority 5
• the TIRTOS clock timer has priority 15 (I guess)

In addition I have 2 TIRTOS tasks which just doing a Task_sleep(1) and triggering some GPIOs, so that I see if they are alive.

With this interrupt priorization, the tasks die after some seconds.

Then, when starting ROV, I can see that they suddenly do a Task_sleep(4294949643) which is 0xFFFFBB0B instead of Task_sleep(1). 

Now my assumption is that the RTOS/HAL interrupt handler has a bug, so that some memory regions get overwritten.

Proove: When I turn the priority of my interrupt from 5 to 15, everything works well !

My source code for R5F interrupt creation is as follows:

// This registers an ISR to an event from PRU via SYSBIOS functionality.
// It's required, that the component MAIN2MCU_LVL_INTRTR0 is already configured.
void registerISROnPRUEventViaSysbios()
{
    Hwi_Handle hwi0;
    Hwi_Params hwiParams;
    Error_Block eb;

    Error_init(&eb);
    Hwi_Params_init(&hwiParams);
    hwiParams.arg = 0;
    hwiParams.enableInt = true;
    hwiParams.priority = 5;   // R5F-VIM has priorities from 0 (highest) to 15 (lowest)
                              // 2019-03-29 it works only with priority 15
                              // all other priorities lead to a system hang
                              // is there a conflict with the timer interrupt?
    hwiParams.maskSetting = ti_sysbios_interfaces_IHwi_MaskingOption_ALL; // disable all other interrupts

    hwi0 = Hwi_create(CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_2, pruIrqHandler, &hwiParams, &eb);
    if (hwi0 == NULL) {
        UART_printf("ERROR: Hwi create failed\n");
    }
}

And my R5F interrupt functions is:

// Interrupt Handler PRU to R5F
static void pruIrqHandler(uintptr_t foobar)
{
    // clear the interrupt source in ICSSG2 on INTC
    PRUICSS_pruClearEvent(s_PruHandle,PRU0_ARM_EVENT);

    // clear R5F interrupt
    // Not needed, the R5 Interrupt is cleared in calling function Hwi_dispatchIRQC()
    //Osal_ClearInterrupt(0, CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_2);

    g_u32PruR5fIrqCnt++;

    //GPIO_write(HAL_GPIO_TIMER_IO0,0);
    GPIOPinWrite_v0(CSL_GPIO1_BASE, 88, 0U);
}

In the PRU I use just

// Define the delay between groups of frames
//   200 MHz: 125us is 25000 * 5ns
//   225 MHz: 125us is 28125 * 4.444ns
#define DELAY_BETWEEN_FRAME_GROUPS	28125

    while(1) {

        // Wait for 125us
        while (PRU0_CTRL.CYCLE < DELAY_BETWEEN_FRAME_GROUPS);
        PRU0_CTRL.CYCLE = 0;

        gpio1PinSet(88);  // set TIMER_IO0 (pin 88)

        // trigger ARM interrupt
        // set bit0 for Host Int0
        // set bit5 for strobe/enable of bit0...3
        __R31 = 0x21;   // trigger host interrupt

        sharedMemPtr->u32Debug1++;
    }

Of course I configured the interrupt router according to E2E entry https://e2e.ti.com/support/processors/f/791/p/784653/2904469

What do you think?

Could this be a bug in the TIRTOS or R5F/HAL interrupt ecosystem?

Best regards,

  Rüdiger

Part Number:TDA2SX

Hi everyone,
I have model trained in Caffe framework and want to convert it using TIDL converter. From TIDL documentation I read that dense convolution flow is supported for only 1x1 and 3x3 kernels with stride = 1
and dilation =1. Also I read about conv2DKernelType parameter for conversion process: conv2DKernelType can be either 0 or 1 for each layer. Default value is 0 for all the layers. Set it to 0 to use sparse convolution, otherwise, set it to 1 to use dense convolution.
In prototxt file of my model, I noticed that stride is set to 2.
So, if conv2DKernelType is by default 0, sparse convolution is used for all layers, there shouldn't be any limitations regarding above mentioned, right? I also tested version where I set conv2DKernelType values for layers to 1, to use dense convolution, which is clearly not supported and I got the same output like for sparse convolution.
So my question is, can we influence type of convolution with conv2DKernelType parameter?

Another thing I noticed is that when processing sample frame some negative values could be seen for sparsity attribute. Can someone explain what this attribute mean and why there are negative values?

 Layer    1 : Out Q :       28 , TIDL_ConvolutionLayer, PASSED  #MMACs =    19.44,    12.87, Sparsity :  33.80
 Layer    2 : Out Q :       11 , TIDL_ConvolutionLayer, PASSED  #MMACs =     6.48,     6.48, Sparsity :   0.00
 Layer    3 : Out Q :        3 , TIDL_ConvolutionLayer, PASSED  #MMACs =    46.08,    27.54, Sparsity :  40.23
 Layer    4 : Out Q :        9 , TIDL_ConvolutionLayer, PASSED  #MMACs =     3.24,     3.24, Sparsity :   0.00
 Layer    5 : Out Q :        4 , TIDL_ConvolutionLayer, PASSED  #MMACs =    46.08,    49.81, Sparsity :  -8.11
 Layer    6 : Out Q :       17 , TIDL_ConvolutionLayer, PASSED  #MMACs =     6.48,     6.48, Sparsity :   0.00
 Layer    7 : Out Q :       27 , TIDL_ConvolutionLayer, PASSED  #MMACs =    92.16,   100.10, Sparsity :  -8.62
 Layer    8 : Out Q :       53 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.66,     1.66, Sparsity :   0.00
 Layer    9 : Out Q :       51 , TIDL_ConvolutionLayer, PASSED  #MMACs =    47.32,    53.86, Sparsity : -13.82
 Layer   10 : Out Q :       62 , TIDL_ConvolutionLayer, PASSED  #MMACs =     3.33,     3.33, Sparsity :   0.00
 Layer   11 : Out Q :       87 , TIDL_ConvolutionLayer, PASSED  #MMACs =    94.63,   106.89, Sparsity : -12.95
 Layer   12 : Out Q :       74 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.83,     0.83, Sparsity :   0.00
 Layer   13 : Out Q :      126 , TIDL_ConvolutionLayer, PASSED  #MMACs =    47.32,    47.28, Sparsity :   0.07
 Layer   14 : Out Q :      136 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.66,     1.66, Sparsity :   0.00
 Layer   15 : Out Q :      195 , TIDL_ConvolutionLayer, PASSED  #MMACs =    94.63,    94.55, Sparsity :   0.09
 Layer   16 : Out Q :       39 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.66,     1.66, Sparsity :   0.00
 Layer   17 : Out Q :      278 , TIDL_ConvolutionLayer, PASSED  #MMACs =    94.63,    94.47, Sparsity :   0.18
 Layer   18 : Out Q :      333 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.66,     1.66, Sparsity :   0.00
 Layer   19 : Out Q :      399 , TIDL_ConvolutionLayer, PASSED  #MMACs =    94.63,    94.26, Sparsity :   0.40
 Layer   20 : Out Q :      527 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.66,     1.66, Sparsity :   0.00
 Layer   21 : Out Q :      473 , TIDL_ConvolutionLayer, PASSED  #MMACs =    94.63,    94.39, Sparsity :   0.25
 Layer   22 : Out Q :      392 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.66,     1.66, Sparsity :   0.00
 Layer   23 : Out Q :      604 , TIDL_ConvolutionLayer, PASSED  #MMACs =    94.63,    93.11, Sparsity :   1.61
 Layer   24 : Out Q :      368 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.46,     0.46, Sparsity :   0.00
 Layer   25 : Out Q :     1064 , TIDL_ConvolutionLayer, PASSED  #MMACs =    52.43,    51.40, Sparsity :   1.96
 Layer   26 : Out Q :      980 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.92,     0.92, Sparsity :   0.00
 Layer   27 : Out Q :      898 , TIDL_ConvolutionLayer, PASSED  #MMACs =   104.86,    96.04, Sparsity :   8.41
 Layer   28 : Out Q :     2131 , TIDL_ConvolutionLayer, PASSED  #MMACs =    26.21,    23.14, Sparsity :  11.72
 Layer   29 : Out Q :     2516 , TIDL_ConvolutionLayer, PASSED  #MMACs =    29.49,    21.24, Sparsity :  27.97
 Layer   30 : Out Q :     6026 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.64,     1.64, Sparsity :   0.05
 Layer   31 : Out Q :     3333 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.65,     2.52, Sparsity :   5.17
 Layer   32 : Out Q :     6666 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.29,     0.29, Sparsity :   1.09
 Layer   33 : Out Q :     5288 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.18,     0.90, Sparsity :  23.39
 Layer   34 : Out Q :     6182 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.07,     0.07, Sparsity :   0.27
 Layer   35 : Out Q :     5659 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.07,     0.03, Sparsity :  58.08
 Layer   36 : Out Q :      274 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.22,     2.79, Sparsity : -25.91
 Layer   37 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
 Layer   38 : Out Q :      771 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.11,     1.11, Sparsity :   0.00

Thanks in advanse,
Sasa

Part Number:AM3352

Tool/software: Linux

Hi Team,

I have a customer who has a few questions about the MMC interface of the AM3352. Question is below:

We use your Sitara CPU (AM3352BZCZD80, AM3352BZCZD30). The eMMC Flash parts that we used at that time are slowly being discontinued. 

Can you tell me:
1. Which JEDEC standard is supported by the HW of the CPU (4.41, 4.5, 5.0?)
2. Which JEDEC standard is supported by the Linux driver? Was there any change in the past? The question is that some of our customers are using an old Linux kernel (3.x), would new eMMC building blocks also work?
3. Did you internally do a compatibility test with the CPU and eMMC devices from different manufacturers? Do we have any results that we could share?
4. Any suggestions from TI how to deal with the discontinuations of eMMC flash?

Regards
Mihir

Part Number:OMAP-L138

Tool/software: TI-RTOS

Hi All.

Now I'm develop feature ARM put DSP into sleep mode in OMAPL138.

I had done put DSP into sleep mode by ARM of OMAPL138. But When I wake DSP up by ARM, DSP not wakeup, and after DSP not working. I don't understand why?

I follow the steps detailed in 10.7.4 C674x Megamodule Clock ON/OFF of SPRUH77.

Here is MY Code:

ARM code:

/*****************************************************************************
 * @file        main.c
 * @author      
 * @version     V0.0.1
 * @date        
 * @brief       
 * @revision
 *****************************************************************************/

/******************************************************************************
 **                               INCLUDES
 ******************************************************************************/
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Queue.h>
#include <ti/sysbios/knl/Semaphore.h>
#include "main.h"
#include "interrupt.h"
#include "delay.h"
#include "lcdkOMAPL138.h"


/* static function */
static void pmu_DSPExitSleepMode (void);
static void pmu_DSPEnterSleepMode (void);

/* Main function */
void main(void)
{
	while(1)
	{
		pmu_DSPEnterSleepMode();
		delay(10000);// delay 10s
		pmu_DSPExitSleepMode();
		delay(10000);// delay 10s	
	}
}


/*******************************************************************************
 ** @brief      sleep DSP
 ** @param      None
 ** @return     None
 ** @time       1:51 PM Friday, March 29, 2019
 ** @revision
 ******************************************************************************/
static void pmu_DSPEnterSleepMode (void)
{
    volatile unsigned int timeout = 0xFFFFFF;
    unsigned int    status = 0;
    unsigned int    regTmp = 0;
    SOS_DEBUG("ARM: set dsp sleep\r\n");
    //PSCModuleControl_1(SOC_PSC_0_REGS, HW_PSC_DSP, PSC_POWERDOMAIN_PD_DSP,\
            PSC_MDCTL_NEXT_DISABLE);

    /* C674x Megamodule Clock OFF */
    /* Step 1: The ARM stops all masters from accessing the DSP and DSP memory */

    /* Step 2: The ARM polls all masters for write-completion status */

    /* Step 3: ARM initiates the following DSP clock shutdown procedure*/

    /* Step 3a: DSP clock stop command */
    regTmp = (HWREG(SOC_PSC_0_REGS +  PSC_MDCTL(HW_PSC_DSP)) & ~PSC_MDCTL_NEXT);
    HWREG(SOC_PSC_0_REGS +  PSC_MDCTL(HW_PSC_DSP)) = regTmp | PSC_MDCTL_NEXT_DISABLE;

    /* step 3b: Write 1 to GO[1] bit */
    HWREG(SOC_PSC_0_REGS + PSC_PTCMD) =  HWREG(SOC_PSC_0_REGS + PSC_PTCMD) | PSC_PTCMD_GO1;

    /* step 3c: Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) */
    do
    {
        status = HWREG(SOC_PSC_0_REGS + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT1;
    }
    while (status && timeout--);
    /* step 3d: Check (poll for 2h) the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15) */
    if (timeout != 0)
    {
        timeout = 0xFFFFFF;
        status = PSC_MDCTL_NEXT_DISABLE;
        do
        {
            timeout--;
        }
        while(timeout && (HWREG(SOC_PSC_0_REGS + PSC_MDSTAT(HW_PSC_DSP)) & PSC_MDSTAT_STATE) != status);
    }

    if (timeout == 0)
    {
    	SOS_DEBUG("ARM: set dsp sleep Fail!\r\n");
    }
    else
    {
    	SOS_DEBUG("ARM: set dsp sleep DONE!\r\n");
    }
}

/*******************************************************************************
 ** @brief      sleep DSP
 ** @param      None
 ** @return     None
 ** @time       1:56 PM Friday, March 29, 2019
 ** @revision
 ******************************************************************************/
static void pmu_DSPExitSleepMode (void)
{

	SOS_DEBUG("ARM: wakeup dsp\r\n");

	volatile unsigned int timeout = 0xFFFFFF;
	unsigned int    status = 0;
	unsigned int    regTmp = 0;
    /* C674x Megamodule Clock ON */
    /* step 1: Wait for the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) to clear to 0. */
	do
	{
		status = HWREG(SOC_PSC_0_REGS + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT1;
		SOS_DEBUG(".\r\n");
	}
	while (status && timeout--);
    /* step 2: Write a 3h to the NEXT bit field in the DSP local power sleep controller (LPSC) module control register (PSC0.MDCTL15)*/
    regTmp = (HWREG(SOC_PSC_0_REGS +  PSC_MDCTL(HW_PSC_DSP)) & ~PSC_MDCTL_NEXT);
    HWREG(SOC_PSC_0_REGS +  PSC_MDCTL(HW_PSC_DSP)) = regTmp | PSC_MDCTL_NEXT_ENABLE;

    /* step 3: Write a 1 to the GO[1] bit */
    HWREG(SOC_PSC_0_REGS + PSC_PTCMD) =  HWREG(SOC_PSC_0_REGS + PSC_PTCMD) | PSC_PTCMD_GO1;

    /* step 4: Check (poll for 0) the GOSTAT[1] bit in PSC0.PTSTAT */
    timeout = 0xFFFFFF;
    do
    {
        status = HWREG(SOC_PSC_0_REGS + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT1;
    }
    while (status && timeout--);

    /* step 5: Wait for the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15) to change to 3h.*/
    if (timeout != 0)
    {
        timeout = 0xFFFFFF;
        status = PSC_MDCTL_NEXT_ENABLE;
        do
        {
            timeout--;
        }
        while(timeout && (HWREG(SOC_PSC_0_REGS + PSC_MDSTAT(HW_PSC_DSP)) & PSC_MDSTAT_STATE) != status);
    }

    if (timeout == 0)
    {
    	SOS_DEBUG("ARM: wakeup dsp Fail!\r\n");
    }
    else
    {
    	SOS_DEBUG("ARM: wakeup dsp DONE!\r\n");
    }
}

DSP Code:

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Mailbox.h>
#include <ti/sysbios/knl/Task.h>

#include "hw_syscfg0_OMAPL138.h"
#include "hw_types.h"
#include "soc_OMAPL138.h"

#include "middleware/debug/debug.h"
#include "middleware/ipc/ipc.h"

uint32_t isSleepDSP = 0;
uint32_t noSleep = 0;

void main(void)
{
	
	while(1)
	{
               /* toggle LED */
		toggle_LED();
                delay(5000);

	}
}


/*******************************************************************************
 ** @brief     	interrupt handle from POWER DOWN CONTROL
 ** @param     	func_param
 ** @return    	none
 ** @time		
 ** @revision
 ******************************************************************************/
void pdc_IRQHandler(void)
{
	IntEventClear(SYS_INT_PDC_INT);
	/* Write a 0001 5555h to PDCCMD */
    HWREG(SOC_PWRDWN_PDC_REGS)=0x00015555;
    isSleepDSP = 1;
    SOS_DEBUG("pdc interrup\r\n);
    asm("  IDLE");
}
 
/*******************************************************************************
 ** @brief     	interrupt handle from ARM
 ** @param     	func_param
 ** @return    	none
 ** @time		
 ** @revision
 ******************************************************************************/
void ipc_IRQ_handler ()
{

    Hwi_disableInterrupt (5);
    if(isSleepDSP)
    {
    	Wakeup_IRQHandler();
    	isSleepDSP = 0;
		noSleep++;
    	SOS_DEBUG("DSP is sleep, noSleep: %d\r\n",noSleep);
    }
    else
    {
    	SOS_DEBUG("DSP is active\r\n");
    }
    Hwi_enableInterrupt (5);
}

note: SOS_DEBUG is my debug function by UART.

The running result : ARM running normal. But DSP print log "pdc interrup" and then DSP does not work.

could someone help me put DSP sleep and wake up it?

Thanks and Best regard!
HUY DAI

Part Number:TMDSICE3359

Dear TI,

My PRU-ICSS TI_ECAT.Patch file cannot patch BECKHOFF SSC 5.12 Src, when running the patch file , it showing these on cmd

C:\patch-2.5.9-7-bin\bin>patch.exe -i C:\ti\PRU-ICSS-EtherCAT_Slave_01.00.07.02\third_party\protocols\ethercat_slave\patch\TI_ECAT.patch -d C:\ti\PRU-ICSS-EtherCAT_Slave_01.00.07.02\protocols\ethercat_slave\ecat_appl\EcatStack
patching file EtherCATSampleLibrary.h
patching file SampleApplicationInterface.c
patching file bootmode.c
Hunk #1 FAILED at 27.
Hunk #2 FAILED at 70.
Hunk #3 FAILED at 88.
3 out of 3 hunks FAILED -- saving rejects to file bootmode.c.rej
patching file cia402appl.c
Reversed (or previously applied) patch detected!  Assume -R? [n] n
Apply anyway? [n] y
Hunk #1 succeeded at 49 with fuzz 2 (offset -7 lines).
Hunk #2 succeeded at 133 with fuzz 2 (offset 25 lines).
Hunk #3 FAILED at 388.
Hunk #4 FAILED at 416.
Hunk #5 FAILED at 426.
Hunk #6 FAILED at 442.
Hunk #7 FAILED at 464.
Hunk #8 FAILED at 500.
Hunk #9 FAILED at 520.
Hunk #10 FAILED at 535.
Hunk #11 succeeded at 631 with fuzz 1 (offset 29 lines).
Hunk #12 FAILED at 786.
Hunk #13 FAILED at 959.
Hunk #14 FAILED at 1657.
Hunk #15 succeeded at 1278 with fuzz 2 (offset -374 lines).
11 out of 15 hunks FAILED -- saving rejects to file cia402appl.c.rej
patching file cia402appl.h
patching file coeappl.c
patching file ecat_def.h
Hunk #2 FAILED at 37.
Hunk #3 FAILED at 59.
Hunk #4 FAILED at 85.
Hunk #5 FAILED at 103.
Hunk #6 FAILED at 143.
Hunk #7 FAILED at 201.
Hunk #8 succeeded at 225 with fuzz 1 (offset -4 lines).
Hunk #9 FAILED at 331.
Hunk #10 FAILED at 343.
Hunk #11 FAILED at 360.
Hunk #12 succeeded at 432 (offset -8 lines).
Hunk #13 succeeded at 462 (offset -8 lines).
Hunk #14 succeeded at 492 (offset -8 lines).
Hunk #15 FAILED at 814.
Hunk #16 FAILED at 826.
Hunk #17 FAILED at 838.
Hunk #18 FAILED at 921.
Hunk #19 FAILED at 937.
Hunk #20 FAILED at 969.
Hunk #21 succeeded at 1050 (offset -68 lines).
15 out of 21 hunks FAILED -- saving rejects to file ecat_def.h.rej
patching file ecatappl.c
Hunk #1 FAILED at 159.
Hunk #2 FAILED at 239.
Hunk #3 FAILED at 754.
Hunk #4 FAILED at 804.
Hunk #5 FAILED at 2045.
Hunk #6 FAILED at 2071.
Hunk #7 FAILED at 2097.
Hunk #8 FAILED at 2120.
8 out of 8 hunks FAILED -- saving rejects to file ecatappl.c.rej
patching file ecatslv.c
Hunk #1 FAILED at 236.
Hunk #2 FAILED at 2613.
2 out of 2 hunks FAILED -- saving rejects to file ecatslv.c.rej
patching file ecatslv.h
Hunk #1 FAILED at 50.
1 out of 1 hunk FAILED -- saving rejects to file ecatslv.h.rej

version not compatible? how can I solve it?

Many thanks for the help!

Best regards

Haowen