Part Number:TMS320C6747

Hi,

In my design we are using TMS320C6747(DSP) processor with External NOR flash,Can we program the external NOR flash using JTAG.

Part Number:PROCESSOR-SDK-OMAPL138

Dear TI team,

I am trying to create a DSP application base uart_c674x project example in Starterware SDK.

In debug mode (JTAG XDS100 V3.0), this application can run normally.

But, when I write the app to Flash, It always stops in IntDSPINTCInit() function.

After research, I found that the app can not access to ISTP register.

I checked the Execution Modes of the device by reading the TSR register. The value is 0x13, so CXM value is 0 mean Supervisor mode.

But, I still can not access to ISTP register.

Could you help me to resolve this issue? I attached my source code.(Please visit the site to view this file)

Regard,

Quy

Part Number:TDA3XEVM

Tool/software: Code Composer Studio

Hi

I debug a program from "C:\PROCESSOR_SDK_VISION_03_03_00_00\ti_components\drivers\pdk_01_09_00_17\packages\ti\drv\stw_lld\examples\dcan\dcanEvmLoopback"

Then the errStatus which the register of DCAN_ES is 0x00000062,

Which mean the format error.

I use the debug tool of CAN bus, which format should I follow to solved this question!!!

Thank you!!!!!!

Part Number:AM4378

Tool/software: Linux

Dear sir,

What I want to do is to create two functions. 'A' function is running at every 1 msec period of time and 'B' function is running at 8 msec period of time.

The execution time for both functions, of course, will be much less than the expected time.

The condition for 'A' function is non-interruptable by any other event, such as keyboard, ethernet, or any thread.... The 'B' function is interruptable by previously stated events .

Is there any way to implement the above goal in linux system ?  

Your response will be highly appreciated, Thank you.

Best regards,

Rechard 

Part Number:TMS320C6713B

Tool/software: TI-RTOS

Hi,

I have a project (without BIOS) for C6713 processor. I am trying to port code written for C6713 DSP processor from baremetal to DSP/BIOS v5.31.2 based. I have few ICs (CAN controller etc.) mapped on  CE0 space of c6713. When i configure them using the old code (without bios) it works fine but when i try to initialize these from main while BIOS configuraiton files included to the project, the CE0 space doesn't seems to be configuring external devices on CE0. Following is rough code:

int main () {

   //initialize CE0 space for asynchronous memory access

  initCE0();

//BIOS_start(); ---> to be called by the kernel.

}

I am totally confused what's the connection b/w BIOS kernel and CE0 EMIF space. Do i have to do some memory configurations in the .tcf config file for CE0??

I compared register setting for both code for CE0 of EMIF. both are same.

Impatiently waiting for your kind response.

Kind Regards,

Tool/software: Linux

Where can I download the sdk "ti-processor-sdk-linux-am335x-evm-04.03.00.05"?

Part Number:PROCESSOR-SDK-AM335X

Tool/software: Linux

I am looking for turning off USB power. I want to turn off the power of the MUSB module on AM335x to save power.

I found similar thread in e2e forums  

I am facing problem in below step 

#echo 0 > /sys/kernel/debug/musb-hdrc.0/softconnect

After that if I do cat I am getting -1

#cat /sys/kernel/debug/musb-hdrc.0/softconnect

-1

 #grep -i 'power\|devctl' /sys/kernel/debug/musb-hdrc.0/regdump

Power : e0
DevCtl : 80

Can you help me on this

Part Number:PROCESSOR-SDK-DRA7X

Tool/software: TI-RTOS

Hi,

Our C, C++ application -- for TDA2XX / EVMDRA75X that is implemented with TI_RTOS and that which involves NIMU + QSPI + UART components from the PDK_DRA7X_1_0_10 -- has run-time problems due to the usage of printf statements.

The application executable is around 6.5MB and the execution intermittently stalls for few seconds to minutes - in our observation/debugging we see that the printf (C-statement) causes such problems.

Kindly share details on how to overcome this. One more issue is that, due to memory constraints we are not including all modules in CCS for this application and so the "system_printf" call is not possible as-of-now.

Quicker and specific response is appreciated.

Thanks,

Sathiyan

Part Number:AM5728

Tool/software: Linux

Hi,

I am Using AM5728 EVM Board Video Loop Back Testing through serial terminal required without GUI?

I have video loop back code from example applications i am taken.

But in loopback code Make.build, mainpro,main.cpp,jpeg.c different files are there how to compile total loop back project?

Before Loop Back Project how to export arm-linux-gnueabihf- compiler and where to export?

How to create videoloopback.out image using arm-linux-gnueabihf- how to run?

Give me some commands for single example project(video loop back) running (/home/root/Loopback/Make.Build files)?

Thanking You,

Ram

Part Number:BEAGLEBK

Tool/software: TI-RTOS

Hi,

I am using the following products for my proejct:

EDMA3 Low Level Driver 2.12.5

NDK 3.40.1.01

SYS/BIOS 6.73.1.01

am335x PDK 1.0.13

Base Example: NIMU_BasicExample_bbbAM335x_armExampleProject

Based on the above example, I created a client server application. It works good. The code below is from cpsw_nimu_eth.c. At the start of the emac driver (NIMU_start), the TxFree variable is set to zero. However, at the time of send the TxFree variable is already set to 1. I wish to know who sets the TxFree variable?

/**
 *   @file  cpsw_nimu_eth.c
 *   @brief
 *     cpsw nimu implementation for AMxxx SOCs
 */

/* Copyright (C) {2012-2017} Texas Instruments Incorporated - http://www.ti.com/ 
 *
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#include <ti/transport/ndk/nimu/src/v4/cpsw_nimu_eth.h>
#include <ti/transport/ndk/nimu/src/NIMU_drv_log.h>

#include <ti/osal/SemaphoreP.h>
#include <ti/transport/ndk/nimu/src/nimu_osal.h>

#include <ti/drv/emac/emac_drv.h>
#include <ti/drv/emac/src/v4/emac_drv_v4.h>


#include <ti/csl/hw_types.h>

#ifdef SOC_AM437x
#include <ti/starterware/include/hw/am437x.h>
#include <ti/starterware/include/hw/hw_control_am43xx.h>
#include <ti/starterware/include/hw/hw_cpsw_ale.h>
#endif

#ifdef SOC_AM335x
#include <ti/starterware/include/hw/soc_am335x.h>
#include <ti/starterware/include/hw/hw_control_am335x.h>
#include <ti/starterware/include/hw/hw_cpsw_ale.h>
#endif


#if defined  (SOC_AM574x) || defined  (SOC_AM572x) ||  defined(SOC_AM571x)
#include <ti/csl/soc.h>
#include <ti/csl/csl_cpswAux.h>
#endif

#if defined(SOC_DRA72x) || defined(SOC_DRA75x) || defined(SOC_DRA78x)
#include <ti/csl/soc/am572x/src/cslr_control_core.h>
#include <ti/csl/csl_cpswAux.h>
#endif



#define     NIMU_PKT_MTU_DEFAULT             1518

/* Max Number of EMAC ports */
#define NIMU_NUM_EMAC_PORTS                  ((uint32_t)2U)

/* Number of emac interface instantiated */
static uint32_t numEmacInterfaces = 0U;

/* Array of initialized EMAC packet buffers to handle incoming packets */
static EMAC_PKT_DESC_T rcv_pkt[4] __attribute__ ((aligned (64)));;


NETIF_DEVICE   ptr_device[NIMU_NUM_EMAC_PORTS];

static      NIMU_CpswPdInfo                        *pPDI[NIMU_NUM_EMAC_PORTS]= {0,0};         /* Handle to Device Info for port 2 (eth2)*/


void CpswHwPktTxNext( NIMU_CpswPdInfo *pi );
int32_t CpswHwPktIoctl(NIMU_CpswPdInfo *pi, uint32_t cmd, void* param, uint32_t size);
static EMAC_PKT_DESC_T* nimu_alloc_pkt(uint32_t port_num, uint32_t pkt_size);
static void nimu_free_pkt(uint32_t port_num,EMAC_PKT_DESC_T*    p_pkt_desc);

static void  nimu_rx_pkt_cb (uint32_t port_num, EMAC_PKT_DESC_T*     p_desc);

static int32_t CpswEmacAddrGet(uint32_t addrIdx, NIMU_CpswMacAddr *p);


/* The EMAC Initialization Function. */
int32_t CpswEmacInit (STKEVENT_Handle hEvent);

/* Used to check status of NDK shutdown */
int32_t shutdown_complete;


uint32_t CpswHwPktOpen( NIMU_CpswPdInfo *pi );


SemaphoreP_Params semParams;
void                      *rxSemaphoreHandle;


/* Defines the num of ports, set using boardType */

/**
 * @brief
 *   CPSW_EMAC_DATA
 *
 * @details
 *  The structure is used to store the private data for the
 *  EMAC controller.
 */
typedef struct CPSW_EMAC_DATA_s
{
/**
  * @brief   Private Information
  */
    NIMU_CpswPdInfo      pdi;
}CPSW_EMAC_DATA;


extern void Osal_TaskCreate(void* pCbFn);
static void nimu_task_poll_pkt (uint32_t*  arg0, uint32_t* arg1); /* misra warning */
static void nimu_task_poll_pkt (uint32_t*  arg0, uint32_t* arg1)
{
    emac_poll_pkt(0);
}


/**
 *  @b NIMU_start
 *  @n
 *  The function is used to initialize and start the EMAC
 *  controller and device.
 *
 *  @param[in]  ptr_net_device
 *      NETIF_DEVICE structure pointer.
 *
 *  @retval
 *      Success -   0
 *  @retval
 *      Error   -   <0
 */
static int_fast32_t NIMU_start (NETIF_DEVICE* ptr_net_device); /* misra warning */
static int_fast32_t NIMU_start (NETIF_DEVICE* ptr_net_device)
{
    EMAC_OPEN_CONFIG_INFO_T open_cfg;
    EMAC_CHAN_MAC_ADDR_T        chan_cfg[1];
    CPSW_EMAC_DATA*  ptr_pvt_data;
    EMAC_HwAttrs_V4 emac_cfg;
    int32_t retVal = 0;
    

    /* Get the pointer to the private data */
    ptr_pvt_data = (CPSW_EMAC_DATA *)ptr_net_device->pvt_data;

    /* Call low-level open function */
    if (CpswHwPktOpen(&ptr_pvt_data->pdi) == 0U)
    {
        /* Copy the MAC Address into the network interface object here. */
        mmCopy((void*)(&ptr_net_device->mac_address[0]), (void*)(&ptr_pvt_data->pdi.bMacAddr[0]), 6U);

        /* Set the 'initial' Receive Filter */
        ptr_pvt_data->pdi.Filter = ETH_PKTFLT_ALL;

        /* only need to init emac driver for 1st interface */
        if(ptr_pvt_data->pdi.PhysIdx == 0U)
        {
            EMAC_socGetInitCfg(0, &emac_cfg);
            open_cfg.hwAttrs = (void*)&emac_cfg;
            open_cfg.alloc_pkt_cb = &nimu_alloc_pkt;
            open_cfg.free_pkt_cb = &nimu_free_pkt;
            open_cfg.rx_pkt_cb = &nimu_rx_pkt_cb;
            open_cfg.loop_back = 0;
            open_cfg.master_core_flag = 1;
            open_cfg.max_pkt_size = NIMU_PKT_MTU_DEFAULT;
            open_cfg.mdio_flag = 1;
            open_cfg.num_of_chans = 1;
            open_cfg.num_of_rx_pkt_desc = 128U;
            open_cfg.num_of_tx_pkt_desc = 128U;
            open_cfg.phy_addr = 0; /* get this from hwAttrs */
    
            chan_cfg[0].p_mac_addr = (EMAC_MAC_ADDR_T*)&ptr_pvt_data->pdi.bMacAddr[0];
        
            /* Set the channel configuration */
            chan_cfg[0].chan_num = 0;
            chan_cfg[0].num_of_mac_addrs = 1;
        
            open_cfg.p_chan_mac_addr = &chan_cfg[0];
            if ((emac_open(0U, &open_cfg)) != EMAC_DRV_RESULT_OK)
            {
               
                NIMU_drv_log("EMACInit_Core failed\n");
                retVal = -1;
            }
            else
            {
                Osal_TaskCreate((void*)nimu_task_poll_pkt);
                
                NIMU_drv_log ("EMAC has been started successfully\n");
                retVal = 0;
            }
        }
    }
    else
    {
        
        /* Error: EMAC failed to start. */
        retVal =  -1;
    }
    
    return retVal;
}


/**
 *  @b NIMU_stop
 *  @n
 *  The function is used to de-initialize and stop the EMAC
 *  controller and device.
 *
 *  @param[in]  ptr_net_device
 *      NETIF_DEVICE structure pointer.
 *
 *  @retval
 *      Success -   0
 *  @retval
 *      Error   -   <0
 */
static int_fast32_t NIMU_stop (NETIF_DEVICE* ptr_net_device); /*misra warning */
static int_fast32_t NIMU_stop (NETIF_DEVICE* ptr_net_device)
{
    CPSW_EMAC_DATA*  ptr_pvt_data;
    EMAC_DRV_ERR_E closeRetVal;
    uint32_t count;
    
    /* Get the pointer to the private data */
    ptr_pvt_data = (CPSW_EMAC_DATA *)ptr_net_device->pvt_data;

    closeRetVal = emac_close(0 );
    if( closeRetVal == EMAC_DRV_RESULT_CLOSE_PORT_ERR )
    {
#ifdef DEBUG_STATS
        csl_errors++;
#endif
        NIMU_drv_log1("EMAC Close Returned error %08x\n",i);
    }

   /* Flush out our pending queue */
    count = PBMQ_count(&ptr_pvt_data->pdi.PBMQ_rx);
    while(count)
    {
        PBM_free( PBMQ_deq(&ptr_pvt_data->pdi.PBMQ_rx) );
        count = PBMQ_count(&ptr_pvt_data->pdi.PBMQ_rx);
    }
    shutdown_complete = 1;

    /* EMAC Controller has been stopped. */
    return 0;
}


/**
 *  @b NIMU_Poll
 *  @n
 *  The function is used to poll the EMAC controller to check
 *  if there has been any activity
 *
 *  @param[in]  ptr_net_device
 *      NETIF_DEVICE structure pointer.
 *  @param[in]  timer_tick
 *      Flag to poll the driver.
 *
 *  @retval
 *      void
 */
static void NIMU_Poll (NETIF_DEVICE* ptr_net_device, uint32_t timer_tick); /* misra warning */
static void NIMU_Poll (NETIF_DEVICE* ptr_net_device, uint32_t timer_tick)
{
    EMAC_LINK_INFO_T info;
    CPSW_EMAC_DATA*  ptr_pvt_data;
    uint32_t port_num;

      /* Get the pointer to the private data  to poll specified port */
        ptr_pvt_data = (CPSW_EMAC_DATA *)ptr_net_device->pvt_data;
      
    /* If running in SWITCH mode, need to call poll routine for both ports to see if any link is up */
    if (numEmacInterfaces == 1U)
   {
       
        if(timer_tick)
        {   
            memset(&info,0, sizeof(EMAC_LINK_INFO_T));
            emac_poll(0U, &info);
            if(info.link_status != EMAC_LINKSTATUS_NOLINK)
            {
                ptr_pvt_data->pdi.TxFree =1;
                CpswHwPktTxNext(&ptr_pvt_data->pdi);
            }
            else
            {
                memset(&info,0, sizeof(EMAC_LINK_INFO_T));
                emac_poll(1U, &info);
                if(info.link_status != EMAC_LINKSTATUS_NOLINK)
                {
                    ptr_pvt_data->pdi.TxFree =1;
                    CpswHwPktTxNext(&ptr_pvt_data->pdi);
                }
            }
        }
    }
    else
    {
        port_num = ptr_pvt_data->pdi.PhysIdx;
        if(timer_tick)
        {
            memset(&info,0, sizeof(EMAC_LINK_INFO_T));
            emac_poll(port_num, &info);
            if(info.link_status != EMAC_LINKSTATUS_NOLINK)
            {
                ptr_pvt_data->pdi.TxFree =1;
                CpswHwPktTxNext(&ptr_pvt_data->pdi);
            }
        }
    }
}

/**
 *  @b NIMU_send
 *  @n
 *  The function is the interface routine invoked by the NDK stack to
 *  pass packets to the driver.
 *
 *  @param[in]  ptr_net_device
 *      NETIF_DEVICE structure pointer.
 *  @param[in]  hPkt
 *      Packet to be sent out on wire.
 *
 *  @retval
 *      Success -   0
 *  @retval
 *      Error   -   <0
 */
static int_fast32_t NIMU_send (NETIF_DEVICE* ptr_net_device, PBM_Handle hPkt); /* misra warning */
static int_fast32_t NIMU_send (NETIF_DEVICE* ptr_net_device, PBM_Handle hPkt)
{

    
    CPSW_EMAC_DATA*  ptr_pvt_data;

    /* Get the pointer to the private data */
    ptr_pvt_data = (CPSW_EMAC_DATA *)ptr_net_device->pvt_data;

    /* Make sure the driver does not transmit packet less than min. as per the
     * Ethernet standards. */
    if( PBM_getValidLen(hPkt) < 60U )
    {
        PBM_setValidLen (hPkt, 60U );
    }
    /* We do not do any packet size checks here. If the packet
     * is too big to fit in the MTU configured on the peripheral,
     * then the driver/CSL layer catches the error.
     */
    
      if(ptr_pvt_data->pdi.TxFree )
     {
          
        /* Enqueue the packet and send it for transmission. */
        PBMQ_enq (&ptr_pvt_data->pdi.PBMQ_tx, hPkt);
        
        /* Pass the packet to the controller if the transmitter is free. */
        CpswHwPktTxNext(&ptr_pvt_data->pdi);
        
    }

      
    /* Packet has been successfully transmitted. */
    return 0;
}


/**
 *  @b NIMU_pktService
 *  @n
 *  The function is called by the NDK core stack to receive any packets
 *  from the driver.
 *
 *  @param[in]  ptr_net_device
 *      NETIF_DEVICE structure pointer.
 *
 *  @retval
 *      void
 */
static void NIMU_pktService (NETIF_DEVICE* ptr_net_device); /* misra warning */
static void NIMU_pktService (NETIF_DEVICE* ptr_net_device)
{

    CPSW_EMAC_DATA*  ptr_pvt_data;
    PBM_Handle          hPacket;
    
    /* Get the pointer to the private data */
    ptr_pvt_data = (CPSW_EMAC_DATA *)ptr_net_device->pvt_data;

    /* Give all queued packets to the Ether module */
    while (PBMQ_count(&ptr_pvt_data->pdi.PBMQ_rx))
    {

        /* Dequeue a packet from the driver receive queue. */
        hPacket = PBMQ_deq(&ptr_pvt_data->pdi.PBMQ_rx);

        /* Prepare the packet so that it can be passed up the networking stack.
         * If this 'step' is not done the fields in the packet are not correct
         * and the packet will eventually be dropped.  */
        PBM_setIFRx (hPacket, ptr_net_device);

        /* Pass the packet to the NDK Core stack. */
        NIMUReceivePacket(hPacket);
#ifdef DEBUG_STATS
        cpsw_raweth_stat.nimuRxCnt++;
#endif
    }

    /* Work has been completed; the receive queue is empty... */
    return;
}


/**
 *  @b NIMU_ioctl 
 *  @n
 *  The function is called by the NDK core stack to configure the
 *  driver
 *
 *  @param[in]  ptr_net_device
 *      NETIF_DEVICE structure pointer.
 *  @param[in]  cmd
 *      Ioctl command.
 *  @param[in]  pBuf
 *      Mac address to be added or deleted.
 *  @param[in]  size
 *      Size of Mac Address.
 *
 *  @retval
 *      Success -   0
 *  @retval
 *      Error   -   <0
 */
static int_fast32_t NIMU_ioctl (NETIF_DEVICE* ptr_net_device, uint32_t cmd, void* pBuf, uint32_t size);/* misra warning */
static int_fast32_t NIMU_ioctl (NETIF_DEVICE* ptr_net_device, uint32_t cmd, void* pBuf, uint32_t size)
{
    CPSW_EMAC_DATA*  ptr_pvt_data;
    int32_t retVal;
    /* Get the pointer to the private data */
    ptr_pvt_data = (CPSW_EMAC_DATA *)ptr_net_device->pvt_data;

    /* call the switch driver's Ioctl handler to take care of this. */
    retVal = CpswHwPktIoctl(&ptr_pvt_data->pdi, cmd, pBuf, size);
    return retVal;
}

/**
 *  @b CpswEmacInit
 *  @n
 *  The function is used to initialize and register the EMAC
 *  with the Network Interface Management Unit (NIMU)
 *
 *  @param[in]  hEvent
 *      Stack Event Handle.
 *
 *  @retval
 *      Success -   0
 *  @retval
 *      Error   -   <0
 */
int32_t CpswEmacInit(STKEVENT_Handle hEvent)
{
    int32_t retVal = 0;
    CPSW_EMAC_DATA*      ptr_pvt_data;
    EMAC_HwAttrs_V4 emac_cfg;
    /* memset netif device struct */
    
    mmZeroInit((void*)(&ptr_device[numEmacInterfaces]), sizeof(NETIF_DEVICE));

    /* Allocate memory for the private data */
    ptr_pvt_data = mmAlloc(sizeof(CPSW_EMAC_DATA));
    if (ptr_pvt_data == NULL)
    {
        NIMU_drv_log ("Error: Unable to allocate private memory data\n");
        retVal= -1;
    }
    else
    {
        /* Initialize the allocated memory block for private data. */
        mmZeroInit (ptr_pvt_data, sizeof(CPSW_EMAC_DATA));

        /* Initialize the RX Queue */
        PBMQ_init(&ptr_pvt_data->pdi.PBMQ_rx);

       /* Retrieve MAC address */
        CpswEmacAddrGet((numEmacInterfaces+1U), (NIMU_CpswMacAddr*)(&( ptr_pvt_data->pdi.bMacAddr[0])));
        /* Set physical index */
        ptr_pvt_data->pdi.PhysIdx = numEmacInterfaces;
        ptr_pvt_data->pdi.hEvent  = hEvent;
        /* MCast List is EMPTY */
        ptr_pvt_data->pdi.MCastCnt    = 0;

        /* Populate the Network Interface Object. */
        if (numEmacInterfaces == 0U)
        {
            strcpy (ptr_device[numEmacInterfaces].name, "eth0");
        }
        else
        {
            strcpy (ptr_device[numEmacInterfaces].name, "eth1");
        }
        ptr_device[numEmacInterfaces].mtu         = ETH_MAX_PAYLOAD - ETHHDR_SIZE;
        ptr_device[numEmacInterfaces].pvt_data    = (void *)ptr_pvt_data;
    
        /* Populate the Driver Interface Functions. */
        ptr_device[numEmacInterfaces].start       = &NIMU_start;
        ptr_device[numEmacInterfaces].stop        = &NIMU_stop;
        ptr_device[numEmacInterfaces].poll        = &NIMU_Poll;
        ptr_device[numEmacInterfaces].send        = &NIMU_send;
        ptr_device[numEmacInterfaces].pkt_service = &NIMU_pktService;
        ptr_device[numEmacInterfaces].ioctl       = &NIMU_ioctl;
        ptr_device[numEmacInterfaces].add_header  = &NIMUAddEthernetHeader;
    
        /* Register the device with NIMU */
        if (NIMURegister (&ptr_device[numEmacInterfaces]) < 0)
        {
            NIMU_drv_log ("Error: Unable to register the EMAC\n");
            retVal = -1;
        }
        else
        {
            numEmacInterfaces++;
            if (numEmacInterfaces == 2U)
            {
                 /* for dualMacMode, need to enableAleBypass */
                EMAC_socGetInitCfg(0, &emac_cfg);
#if defined (SOC_AM335x) || defined(SOC_AM437x)
               
                HW_WR_FIELD32((emac_cfg.ale_base +  CPSW_ALE_CTRL),
                CPSW_ALE_CTRL_BYPASS, CPSW_ALE_CTRL_BYPASS_ENABLE);
#else
    CSL_CPSW_enableAle((CSL_cpswHandle)emac_cfg.ss_base);
#endif
                NIMU_drv_log ("Registeration of the EMAC Successful\n");
                retVal = 0;
            }
        }
    }
     return retVal;
}



/**
 *  @b RxPacket
 *  @n
 *      Function called by CSL to pass the received packet to the driver.
 *
 *  @param[in]  hApplication
 *      Driver's handle.
 *  @param[in]  cslPkt
 *      CPSW_Pkt type packet passed by CSL.
 *
 *  @retval
 *        EMAC_PKT_DESC_T pointer of a packet with buffer to replenish CSL.
 */
static void  nimu_rx_pkt_cb (uint32_t port_num, EMAC_PKT_DESC_T*     p_desc)
{
    if (numEmacInterfaces == 2U)
    {
        /* Remove the 4 byte header from the packet. Not sure as to why the EMAC
        * is adding an extra 4bytes to the header. This is causing stack to
        * fail checksum validations on IPv6 packets. So, remove the extra 4 bytes
        * tagged by the EMAC.
        */
        if (port_num == 0U)
        {
            PBM_setValidLen((PBM_Handle) p_desc->AppPrivate, (p_desc->ValidLen - 4));
            PBM_setIFRx((PBM_Handle) p_desc->AppPrivate, pPDI[0]->hEther );
    
            PBMQ_enq( &pPDI[0]->PBMQ_rx, (PBM_Handle) p_desc->AppPrivate );
    
            /* Notify NDK stack of pending Rx Ethernet packet */
            STKEVENT_signal( pPDI[0]->hEvent, STKEVENT_ETHERNET, 1U );
        }
        else
        {
            PBM_setValidLen((PBM_Handle) p_desc->AppPrivate, (p_desc->ValidLen - 4));
            PBM_setIFRx((PBM_Handle) p_desc->AppPrivate, pPDI[1]->hEther );
    
            PBMQ_enq( &pPDI[1]->PBMQ_rx, (PBM_Handle) p_desc->AppPrivate );
    
            /* Notify NDK stack of pending Rx Ethernet packet */
            STKEVENT_signal( pPDI[1]->hEvent, STKEVENT_ETHERNET, 1U );
        }
    }
    else
    {
        PBM_setValidLen((PBM_Handle) p_desc->AppPrivate, (p_desc->ValidLen - 4));
        PBM_setIFRx((PBM_Handle) p_desc->AppPrivate, pPDI[0]->hEther );
    
        PBMQ_enq( &pPDI[0]->PBMQ_rx, (PBM_Handle) p_desc->AppPrivate );
    
        /* Notify NDK stack of pending Rx Ethernet packet */
        STKEVENT_signal( pPDI[0]->hEvent, STKEVENT_ETHERNET, 1U );
    }
}

/**
 *  @b Description
 *  @n
 *      Call back function provided by application for EMAC driver
 *      to allocate a packet descriptor.
 *
 *  @retval
 *      pointer to the allocated packet descriptor.
 */
static EMAC_PKT_DESC_T*
nimu_alloc_pkt
(
    uint32_t              port_num,
    uint32_t              pkt_size
)
{
    PBM_Handle hPkt;
    EMAC_PKT_DESC_T* pktDesc;

    /* ADD SIZE CHECK */
    hPkt = PBM_alloc(pkt_size + 4U + NIMU_PKT_PREPAD);
    if (hPkt != NULL)
    {
        PBM_setDataOffset(hPkt,NIMU_PKT_PREPAD);

        rcv_pkt[port_num].AppPrivate   = (uint32_t)hPkt;
        rcv_pkt[port_num].pDataBuffer  = PBM_getDataBuffer(hPkt);
        rcv_pkt[port_num].BufferLen    = PBM_getBufferLen(hPkt);
        rcv_pkt[port_num].DataOffset = PBM_getDataOffset(hPkt);
        rcv_pkt[port_num].pPrev = NULL;
        rcv_pkt[port_num].pNext = NULL;
        pktDesc = &rcv_pkt[port_num];
    }
    else
    {
        pktDesc = NULL;
    }
    return pktDesc;
}

/**
 *  @b Description
 *  @n
 *      Call back function provided by application for EMAC driver
 *      to free a packet descriptor.
 *
 *  @retval
 *      None.
 */
static void
nimu_free_pkt
(
    uint32_t              port_num,
    EMAC_PKT_DESC_T*    p_pkt_desc
)
{
    (void)port_num;
    PBM_free((PBM_Handle)(p_pkt_desc->AppPrivate));
}


/**
 *  @b CpswHwPktOpen
 *  @n
 *      Opens and configures EMAC. Configures Interrupts, SGMII,
 *      and send and receive queues.
 *
 *  @param[in]  pi
 *      PDINFO structure pointer.
 *
 *  @retval
 *      Success -   0
 *  @retval
 *      Error   -   >0
 */
uint32_t CpswHwPktOpen( NIMU_CpswPdInfo *pi )
{

    pPDI[pi->PhysIdx] = pi;

    /* Init internal bookkeeping fields */
    pi->OldMCastCnt = 0U;

    /* Wait for link to come up */
    pi->TxFree = 0U;


    return 0U;
}




/**
 *  @b CpswHwPktTxNext
 *  @n
 *      Routine to send out a packet.
 *
 *  @param[in]  pi
 *      PDINFO structure pointer.
 *
 *  @retval
 *      void
 */
void CpswHwPktTxNext( NIMU_CpswPdInfo *pi )
{
    PBM_Handle          hPkt;
    EMAC_PKT_DESC_T     csl_send_pkt;
    EMAC_DRV_ERR_E sendResult;
    uint32_t portFlag = 0U;

    /* Checking for any queued packets to be transmitted */
    hPkt = PBMQ_deq(&pi->PBMQ_tx);
    if (hPkt == NULL)
    {
        pi->TxFree = 1;
    }
    else
    {
        csl_send_pkt.AppPrivate     = (uint32_t)hPkt;
        csl_send_pkt.pDataBuffer    = PBM_getDataBuffer(hPkt);
        csl_send_pkt.BufferLen      = PBM_getBufferLen(hPkt);
        csl_send_pkt.ValidLen       = PBM_getValidLen(hPkt);
        csl_send_pkt.DataOffset     = PBM_getDataOffset(hPkt);
        csl_send_pkt.pNext = NULL;
        csl_send_pkt.pPrev = NULL;


        csl_send_pkt.Flags          = EMAC_PKT_FLAG_SOP | EMAC_PKT_FLAG_EOP;

        /* for dual emac mode, need to update the flags to direct packet out specified port */
        if(numEmacInterfaces == 2U)
        {
            portFlag = (pi->PhysIdx + 1U) << EMAC_PKT_FLAG_TO_PORT_SHIFT;
            
            csl_send_pkt.Flags  |= portFlag;
        }
            /* We only use one Tx DMA channel  now. If QOS/Priority has to be
             * supported, identify the channel number based on vlan/priority tag or
             * any other field from the header fields of the ethernet frame.
             */
        csl_send_pkt.PktChannel     = 0; 
        csl_send_pkt.PktLength      = PBM_getValidLen(hPkt);
        csl_send_pkt.PktFrags       = 1;
    
    
            sendResult = emac_send(0, &csl_send_pkt);
    
            if(sendResult)
            {
            
                NIMU_drv_log1("CPSW_sendPacket() returned error %08x\n",i);
    
                /* Free the packet as the packet did not go on the wire*/
                PBM_free( (PBM_Handle)csl_send_pkt.AppPrivate );
            }
    }
}


int32_t CpswHwPktIoctl(NIMU_CpswPdInfo *pi, uint32_t cmd, void* param, uint32_t size)
{
    return 0;
}



/**
 * \brief   This function returns the MAC address for the EVM
 *
 * \param   addrIdx    the MAC address index.
 * \param   macAddr    the Pointer where the MAC address shall be stored
 *     'addrIdx' can be either 1 or 2
 *
 * \return  None.
 */
#ifdef SOC_AM437x
static int32_t CpswEmacAddrGet(uint32_t addrIdx, NIMU_CpswMacAddr *p); /* misra warning */
static int32_t CpswEmacAddrGet(uint32_t addrIdx, NIMU_CpswMacAddr *p)
{
    int32_t retVal = 0;
    switch(addrIdx)
    {
        case 1U:
            p->macAddr[5U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID0_LO,
                CTRL_MAC_ID0_LO_MACADDR_7_0);
            p->macAddr[4U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID0_LO,
                CTRL_MAC_ID0_LO_MACADDR_15_8);
            p->macAddr[3U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID0_HI,
                CTRL_MAC_ID0_HI_MACADDR_23_16);
            p->macAddr[2U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID0_HI,
                CTRL_MAC_ID0_HI_MACADDR_31_24);
            p->macAddr[1U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID0_HI,
                CTRL_MAC_ID0_HI_MACADDR_39_32);
            p->macAddr[0U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID0_HI,
                CTRL_MAC_ID0_HI_MACADDR_47_40);
            break;

        case 2U:
            p->macAddr[5U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID1_LO,
                CTRL_MAC_ID1_LO_MACADDR_7_0);
            p->macAddr[4U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID1_LO,
                CTRL_MAC_ID1_LO_MACADDR_15_8);
            p->macAddr[3U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID1_LO,
                CTRL_MAC_ID1_HI_MACADDR_23_16);
            p->macAddr[2U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID1_HI,
                CTRL_MAC_ID1_HI_MACADDR_31_24);
            p->macAddr[1U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID1_HI,
                CTRL_MAC_ID1_HI_MACADDR_39_32);
            p->macAddr[0U] = HW_RD_FIELD32(SOC_CONTROL_MODULE_REG + CTRL_MAC_ID1_HI,
                CTRL_MAC_ID1_HI_MACADDR_47_40);
            break;

        default:
            retVal =  -1;
            break;
    }
    return retVal;
}
#endif

#ifdef SOC_AM335x
static int32_t CpswEmacAddrGet(uint32_t addrIdx, NIMU_CpswMacAddr *p); /* misra warning */
static int32_t CpswEmacAddrGet(uint32_t addrIdx, NIMU_CpswMacAddr *p)
{
    uint32_t slavePortNum = addrIdx - 1U;
    int32_t retVal = 0;

    switch(addrIdx)
    {
        case 1U:
        p->macAddr[5U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(slavePortNum))
                           & CONTROL_MAC_ID0_LO_MACADDR_7_0) >> CONTROL_MAC_ID0_LO_MACADDR_7_0_SHIFT;
        p->macAddr[4U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(slavePortNum)))
                          & CONTROL_MAC_ID0_LO_MACADDR_15_8;
        p->macAddr[3U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(slavePortNum))
                           & CONTROL_MAC_ID0_HI_MACADDR_23_16) >> CONTROL_MAC_ID0_HI_MACADDR_23_16_SHIFT;
        p->macAddr[2U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(slavePortNum))
                           & CONTROL_MAC_ID0_HI_MACADDR_31_24) >> CONTROL_MAC_ID0_HI_MACADDR_31_24_SHIFT;
        p->macAddr[1U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(slavePortNum))
                           & CONTROL_MAC_ID0_HI_MACADDR_39_32) >> CONTROL_MAC_ID0_HI_MACADDR_39_32_SHIFT;
        p->macAddr[0U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(slavePortNum)))
                          & CONTROL_MAC_ID0_HI_MACADDR_47_40;
            break;

        case 2U:
        p->macAddr[5U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(slavePortNum))
                           & CONTROL_MAC_ID0_LO_MACADDR_7_0) >> CONTROL_MAC_ID0_LO_MACADDR_7_0_SHIFT;
        p->macAddr[4U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(slavePortNum)))
                          & CONTROL_MAC_ID0_LO_MACADDR_15_8;
        p->macAddr[3U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(slavePortNum))
                           & CONTROL_MAC_ID0_HI_MACADDR_23_16) >> CONTROL_MAC_ID0_HI_MACADDR_23_16_SHIFT;
        p->macAddr[2U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(slavePortNum))
                           & CONTROL_MAC_ID0_HI_MACADDR_31_24) >> CONTROL_MAC_ID0_HI_MACADDR_31_24_SHIFT;
        p->macAddr[1U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(slavePortNum))
                           & CONTROL_MAC_ID0_HI_MACADDR_39_32) >> CONTROL_MAC_ID0_HI_MACADDR_39_32_SHIFT;
        p->macAddr[0U] =  (HW_RD_REG32(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(slavePortNum)))
                          & CONTROL_MAC_ID0_HI_MACADDR_47_40;
            break;

        default:
            retVal =  -1;
            break;
    }
    return retVal;
}
#endif


#if defined  (SOC_AM574x) || defined  (SOC_AM572x) ||  defined(SOC_AM571x) || defined(SOC_DRA72x) || defined(SOC_DRA75x) || defined(SOC_DRA78x)

static int32_t CpswEmacAddrGet(uint32_t addrIdx, NIMU_CpswMacAddr *p); /* misra warning */
static int32_t CpswEmacAddrGet(uint32_t addrIdx, NIMU_CpswMacAddr *p)
{
    int32_t retVal = 0;

    uint32_t tempVal;
    CSL_control_coreRegs * tempAddr;
    tempAddr =   (CSL_control_coreRegs*)SOC_CTRL_MODULE_CORE_CORE_REGISTERS_BASE;

    switch(addrIdx)
    {
        case 1U:
            tempVal = tempAddr->MAC_ID_SW_1;
            p->macAddr[0U] = (uint8_t)((tempVal >> 16U) & 0xFFU);
            p->macAddr[1U] = (uint8_t)((tempVal >> 8U) & 0xFFU);
            p->macAddr[2U] = (uint8_t)(tempVal & 0xFFU);

            tempVal = tempAddr->MAC_ID_SW_0;
            p->macAddr[3U] = (uint8_t)((tempVal >> 16U) & 0xFFU);
            p->macAddr[4U] = (uint8_t)((tempVal >> 8U) & 0xFFU);
            p->macAddr[5U] = (uint8_t)((tempVal) & 0xFFU);
            break;

        case 2U:

            tempVal = tempAddr->MAC_ID_SW_3;
            p->macAddr[0U] = (uint8_t)((tempVal >> 16U) & 0xFFU);
            p->macAddr[1U] = (uint8_t)((tempVal >> 8U) & 0xFFU);
            p->macAddr[2U] = (uint8_t)(tempVal & 0xFFU);

            tempVal = tempAddr->MAC_ID_SW_2;
            p->macAddr[3U] = (uint8_t)((tempVal >> 16U) & 0xFFU);
            p->macAddr[4U] = (uint8_t)((tempVal >> 8U) & 0xFFU);
            p->macAddr[5U] = (uint8_t)((tempVal) & 0xFFU);
            break;
        default:
            retVal = -1;
            break;
    }
    return retVal;
}
#endif

Part Number:AM5748

Hi,

I saw that the heat sink reference of the AM5728 EVM is  BDN10-3CB/A01 from CTS.

I'm currently using a AM5748 EVM and the Heat sink seems not correspond physically to this reference. It seems to be bigger.

Does anybody knows the reference?

Thanks in advance.

Sylvain.

Part Number:AM6548

Hi,

to make some PRU performance measurements, I would like to use the Cycle Count.

The TRM describe the physical address of PRU_ICSSG_0_PR1_PDSP0_IRAM to 0xB02200. The Cycle Count Register at 0xB0220C. However the memory at these address does not change when PRU is running.

However, after some time I disovered that at address 0xB02200C some data is placed, which could be the Cycle Count Register for ICSSG0_PRU0.
Can you confirm this?
If yes, why is there a 0 missing in the TRM?

Best regards,
Thomas

Part Number:BEAGLEBK

Tool/software: TI-RTOS

Hi,

I am using the following product:

NDK 3.40.1.01

I see that in the source code of NDK, there is a use of DbgPrintf command to print a message to the global debug log buffer. I wish to use this function to print debug warnings and errors. But how can I access these printf statements? Where is the debug log recorded? How can I see this record?

Regards

Vishav

Part Number:AM5K2E02

Hi,

We are working on a prototype board with a AM5K2E02 processor. Our current power down sequence is to power down all rails simultaneously when input power is removed. 

We have measured the rails as they collapse and noticed that CVDD1 is greater than CVDD for roughly 2ms before it falls below CVDD. 

Is this likely to affect long term reliability of the processor?   

The other rails seem fine, but are there any others we should pay special attention to?

I've attached a screen shot of the scope waveforms, yellow trace is CVDD and blue is CVDD1.

Thanks,

Jack

Part Number:TMS320C6678

Hi,

I am using all cores of the C6678 for parallel data processing. The different concurrent tasks issue EDMA requests and wait busily for the respective completion interrupts. It is possible to concurrently issue transfer requests by different DSP cores to the channel controller? Or is there a general limitation with several cores accessing the same EDMA CC?

I use the CSL for the EDMA calls. For this question let's assume that I use only the channel controller CSL_EDMA3_TPCC0.

The program works fine if I use only one core. If several cores are used, interrupts are missed and the system hangs while waiting busily.

• There is at maximum one EDMA transfer ongoing for each core.
• If I ensure mutual exclusive access to the EDMA channel controller (covering the EDMA setup until the completion interrupt), I can safely use up to all eight cores.

I suspect one of the following problems:

• The EDMA CC queues are not initialized correctly.
• There is a problem with the interrupt registration or the assignment of the shadow regions.

Do you see a problem with my EDMA initialization? Is there anything else that has to be done differently?

Thank you!

P.S.: Here are the most important parts of the code I am using:

bool edmaTransfer() { // is called concurrently
    CSL_Edma3Handle hModule;
    CSL_Edma3ChannelHandle hChannel;
    CSL_Edma3CmdIntr regionIntr;
    CSL_Edma3Context context;
    CSL_Edma3Obj edmaObj;
    CSL_Edma3CmdDrae regionAccess;
    CSL_Edma3ChannelAttr chAttr;
    CSL_Edma3ChannelObj chObj;
    CSL_Edma3ParamHandle hParamStart;
    CSL_Status statusCode;

    CSL_InstNum ccNum = 0;

    uint8_t channelNum = ccNum;

    /* Module Initialization */
    if (! initEdmaHandle(channelNum, ccNum,
            context, edmaObj, statusCode, regionAccess, chAttr, chObj, hModule, regionIntr, hChannel, hParamStart)) {
        return false;
    }

    // Set EDMA loop index space
    CSL_Edma3ParamSetup paramSetup;
    if (! setEdmaParams(paramSetup, channelNum)) {
        return false;
    }

    /* Setup the Ping Entry which loaded after the Pong entry gets exhausted */
    if (CSL_edma3ParamSetup(hParamStart,&paramSetup) != CSL_SOK) {
        return false;
    }

    /* Enable channel */
    if (CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL) != CSL_SOK) {
        return false;
    }

    if ((statusCode = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL)) != CSL_SOK) {
        return false;
    }

    do {
        /* Poll on interrupt bit 0 */
        CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND, &regionIntr);
    } while (!(regionIntr.intr & (0x1 << channelNum)));

    /* Clear interrupt bit 0 */
    if (CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, &regionIntr) != CSL_SOK) {
        return false;
    }

    /* Close channel */
    if (CSL_edma3ChannelClose(hChannel) != CSL_SOK) {
        return false;
    }

    /* Close EDMA module */
    if (CSL_edma3Close(hModule) != CSL_SOK) {
        return false;
    }
    return true;
}


bool initEdmaHandle(uint8_t channelNum, CSL_InstNum instNum,
        CSL_Edma3Context& context, CSL_Edma3Obj& edmaObj, CSL_Status& statusCode, CSL_Edma3CmdDrae& regionAccess,
        CSL_Edma3ChannelAttr& chAttr, CSL_Edma3ChannelObj& chObj, CSL_Edma3Handle& hModule,
        CSL_Edma3CmdIntr& regionIntr, CSL_Edma3ChannelHandle& hChannel, CSL_Edma3ParamHandle& hParamStart) {
    int32_t regionNum = DNUM; // core number
    /* Module Initialization */
    if (CSL_edma3Init(&context) != CSL_SOK) {
        return false;
    }
    /* Module level open */
    hModule = CSL_edma3Open(&edmaObj, instNum, NULL, &statusCode);
    if ((hModule == NULL) || (statusCode != CSL_SOK)) {
        return false;
    }
    // sprugs5b 2.9.1:
    // If the channel is used in the context of a shadow region and you intend for the shadow region interrupt to be asserted,
    // then ensure that the bit corresponding to the TCC code is enabled in IER/IERH
    // and in the corresponding shadow region's DMA region access registers (DRAE/DRAEH).
    regionAccess.region = regionNum;
    regionAccess.drae = (0x1 << channelNum);
    regionAccess.draeh = 0x0;
    if (CSL_edma3HwControl(hModule, CSL_EDMA3_CMD_DMAREGION_ENABLE, &regionAccess) != CSL_SOK) {
        return false;
    }

    /* Interrupt enable (Bits 0-11) for the shadow region 5 */
    regionIntr.region = regionNum;
    regionIntr.intr = (0x1 << channelNum);
    regionIntr.intrh = 0x0000;
    if (CSL_edma3HwControl(hModule, CSL_EDMA3_CMD_INTR_ENABLE, &regionIntr) != CSL_SOK) {
        return false;
    }
    /* Open the channel in context of the specified region number. */
    chAttr.regionNum = regionNum;
    chAttr.chaNum = channelNum;
    hChannel = CSL_edma3ChannelOpen(&chObj, instNum, &chAttr, &statusCode);
    if ((hChannel == NULL) || (statusCode != CSL_SOK)) {
        return false;
    }
    int PaRAM_Set = DNUM; // core number
    /* Map the DMA Channel to the appropriate PARAM Block. We start with PING
     * which is located at PARAM Block 1. */
    if (CSL_edma3HwChannelSetupParam(hChannel, PaRAM_Set) != CSL_SOK) {
        return false;
    }
    /* Obtain a handle to parameter set 1 */
    hParamStart = CSL_edma3GetParamHandle(hChannel, PaRAM_Set, &statusCode);
    if (hParamStart == NULL) {
        return false;
    }
    return true;
}


// Calculate index space for EDMA transfer - values like aCnt, bCnt are calculated and stored elsewhere.
bool setEdmaParams(CSL_Edma3ParamSetup& paramSetup, uint8_t channelNum) const {
    // Set EDMA parameters
    paramSetup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, CSL_EDMA3_TCCH_DIS,\
                CSL_EDMA3_ITCINT_DIS, CSL_EDMA3_TCINT_EN, channelNum, CSL_EDMA3_TCC_NORMAL,\
                CSL_EDMA3_FIFOWIDTH_NONE, CSL_EDMA3_STATIC_DIS, CSL_EDMA3_SYNC_AB,\
                CSL_EDMA3_ADDRMODE_INCR, CSL_EDMA3_ADDRMODE_INCR );
    paramSetup.aCntbCnt   = CSL_EDMA3_CNT_MAKE(aCnt, bCnt);
    paramSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(aCnt, aCnt);
    paramSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, 0);
    paramSetup.cCnt = 1;
    paramSetup.linkBcntrld= CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL, 0); // no linked transfer
    paramSetup.srcAddr = reinterpret_cast<uint32_t>(makeAddressGlobal(src));
    paramSetup.dstAddr = reinterpret_cast<uint32_t>(makeAddressGlobal(dest));
    return true;
}

Part Number:AM3352

Hello,

We have an issue during a WARM reset. The board should boot from NAND, but it tries to boot from a Wifi peripheral that s connected to the MMC1 interface.

The MMC0 interface is connected to a SDcard connector and only used in production for initial programming of the on board nand flash.

Our sysboot (4:0) is set to 00100. This means UART0/XIP/MMC0/NAND.

So, in production it boots from MMC0 (SD card), and in the field it boots from NAND.

But once the Wifi slave (connected to MMC1) gets initialized, we have a issue at the next warm reset.

Since it is connected to MMC1, I would not expect any interference in the boot scheme. "00100" never addresses MMC1 as a boot device.

How can we block the attempt to boot from MMC1 ?

Part Number:AM5718

Reference the AM5718 IDK board (http://www.ti.com/tool/tmdxidk5718) schematics, p.5.  It shows a voltage divider on the input to U96.

The signal GPIO_USB2_VBUS_DET then feeds into an AM5718 GPIO on p.32.

Question: What is the need for the voltage divider?

Thank you,

David

Part Number:BEAGLEBK

Tool/software: TI-RTOS

Hi,

I am trying to debug my application and I am getting following exception in ROV (Sysmin-> OutputBuffer view) :

Target memory read failed at address: 0x8004d4f8, length: 12 This read is at a VALID address according to the application's section map, but the DebugServer memory read failed.

Here are the details of tools and products that I am using:

EDMA3 Low Level Driver 2.12.5

NDK 3.40.1.01

SYS/BIOS 6.73.1.01

am335x PDK 1.0.13

xdctools_3_51_01_18

However, I don't see this error if I am using ROV Classic. Is there something wrong in my application? Which tool is better for debugging ROV or ROV Classic?

Regards

Vishav

Part Number:PROCESSOR-SDK-DRA7X

Tool/software: TI-RTOS

Hi,

on running our application ( NIMU + QSPI flash + TI_RTOS ), there is task corruption observed irrespective of increase of the Task Stack sizes in the cfg file.

Herewith attached the ROV views (Callstack, Detailed view, Module - Stackpeak), CFG file and the execution console CIO logs.

Quick look of the crash log is pasted here :

Exception occurred in ThreadType_Task.
Task handle: 0x80117348.
Task stack base: 0x80117398.
Task stack size: 0x8000.
R0 = 0x00000001 R8 = 0xffffffff
R1 = 0x19110300 R9 = 0xffffffff
R2 = 0x8008df1c R10 = 0xffffffff
R3 = 0x00000001 R11 = 0xffffffff
R4 = 0x801172d8 R12 = 0x2000015f
R5 = 0xffffffff SP(R13) = 0x8011ec38
R6 = 0xffffffff LR(R14) = 0x8000a310
R7 = 0xffffffff PC(R15) = 0xfffffffe
PSR = 0x200001df
DFSR = 0x00000000 IFSR = 0x00000210
DFAR = 0x00000000 IFAR = 0xfffffffe
ti.sysbios.family.arm.exc.Exception: line 201: E_prefetchAbort: pc = 0xfffffffe, lr = 0x8000a310.
xdc.runtime.Error.raise: terminating execution

Please refer these and provide us the suggestion to fix this issue - quite urgent & quick/effective solution shall be appreciated. Thanks !

Regards,

Sathiyan

Hello All,

I have a problem with executing SBL from the SD card for AM65xx on AM654x IDK.
My configuration is:

CCS ver 8.3.0
Windows version - Windows 10 Pro version 1803
PDK - pdk_am65xx_1_0_3

I built SBL from the cmd line as instructed in:

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html#am65x

My openssl version is OpenSSL 1.1.0j 20 Nov 2018
Build seemed successful (I attached gmake output). Source was not modified.

I then prepared SD card (used original SD card shipped with IDK) by copying sbl_mmcsd_img_mcu1_0_release.tiimage as tiboot3.bin set the bootmode pins and tried booting.
However, I did not get anything from the MCU UART. If I use original tiboot3.bin everything works as expected.

I checked the map file and it seems ok:

OUTPUT FILE NAME: </ti/pdk_am65xx_1_0_3/packages/ti/boot/sbl/build/../../../../ti/boot/sbl/binary/am65xx_idk/mmcsd/bin/sbl_mmcsd_img_mcu1_0_release.xer5f>
ENTRY POINT SYMBOL: "_sblResetVectors" address: 41c00100

MEMORY CONFIGURATION

name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
RESET_VECTORS 41c00100 00000100 000000d8 00000028 X
OCMRAM_SBL 41c00200 00027e00 00020490 00007970 RWIX
OCMRAM_SBL_SYSFW 41c28000 00040000 00000008 0003fff8 RWIX

SEGMENT ALLOCATION MAP

run origin load origin length init length attrs members
---------- ----------- ---------- ----------- ----- -------
41c00100 41c00100 000000d8 000000d8 r-x
41c00100 41c00100 000000d8 000000d8 r-x .rstvectors
41c00200 41c00200 00010450 00010450 r-x
41c00200 41c00200 00010450 00010450 r-x .text
41c10680 41c10680 00003b80 00000000 rw-
41c10680 41c10680 00003b80 00000000 rw- .data
41c14200 41c14200 00003ad0 00000000 rw-
41c14200 41c14200 00003ad0 00000000 rw- .bss
41c17cd0 41c17cd0 00000e68 00000e68 r--
41c17cd0 41c17cd0 00000e68 00000e68 r-- .const
41c18b80 41c18b80 00000b88 00000b88 r--
41c18b80 41c18b80 00000500 00000500 r-- .boardcfg_data
41c19080 41c19080 00000688 00000688 r-- .cinit
41c21000 41c21000 00005000 00000000 r--
41c21000 41c21000 00000800 00000000 r-- .undStack
41c21800 41c21800 00002000 00000000 r-- .svcStac
41c23800 41c23800 00001000 00000000 r-- .irqStack
41c24800 41c24800 00001000 00000000 r-- .fiqStack
41c25800 41c25800 00000800 00000000 r-- .abortStack
41c26000 41c26000 00002008 00000000 rw-
41c26000 41c26000 00002000 00000000 rw- .stack
41c28000 41c28000 00000008 00000000 rw- .firmware

What am I missing here?

Best regards,

Milan

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