Part Number:AMIC120
Hello,
Does shared memory in PRU-ICSS have any hardware to prevent access collision (accessing at the same time from A9 and PRU core and reading wrong data)?
If yes, could you tell me what it is or any URL described about it?
If no, could you tell me how to prevent access collision in shared memory?
Regards,
U-SK
Part Number:AMIC120
Hello.
I would like to generate interrupt to A9 at the both of peak and zero of PWM timer.
But according to ETSEL bit, it seems that we can choose only one or the other .
Could you tell me how to do it?
Regards,
U-SK
Part Number:PROCESSOR-SDK-AM335X
Tool/software: Linux
We've a custom board based on AM335x-EVM-Starter Kit.
SDK we're using is ti-processor-sdk-linux-am335x-evm-05.00.00.15.
In the above schematic, the following 3 lines are connected to the FPGA.
1. UART1_CTSn,
2. UART1_RTSn &
3. GPMC_BEn0_CLE
Our requirement is to prove the clock rate as 10 MHz on all the above 3 lines.
1. We want to send some buffer from processor (ex:- an array of 1024 bytes) to FPGA and capture the data. How to do it?
2. If any thing to be set in the kernel, where and all I should modify?
Please find below my dts file & the program that I am using to send data to FPGA, Please suggest me changes required, if any.
DTS:
gpio1_pins:gpio1_pins{
pinctrl-single,pins = <
AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE7) /*UART1_CTSn.GPIO0_12*/
AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE7) /*UART1_RTSn.GPIO0_13*/
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7) /*GPMC_BEn0_CLE.GPIO2_5*/
>;
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins>;
status = "okay";
};
Program to send data to FPGA:
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <fcntl.h>
#include <unistd.h>
#include <sys/select.h>
#include <sys/stat.h>
#include <time.h>
#include <getopt.h>
//#include "gpiolib.h"
int gpio_export(int gpio)
{
int efd;
char buf[50];
int gpiofd, ret;
/* Quick test if it has already been exported */
sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio);
efd = open(buf, O_WRONLY);
if(efd != -1) {
close(efd);
return 0;
}
efd = open("/sys/class/gpio/export", O_WRONLY);
if(efd != -1) {
sprintf(buf, "%d", gpio);
ret = write(efd, buf, strlen(buf));
if(ret < 0) {
perror("Export failed");
return -2;
}
close(efd);
} else {
// If we can't open the export file, we probably
// dont have any gpio permissions
return -1;
}
return 0;
}
void gpio_unexport(int gpio)
{
int gpiofd, ret;
char buf[50];
gpiofd = open("/sys/class/gpio/unexport", O_WRONLY);
sprintf(buf, "%d", gpio);
ret = write(gpiofd, buf, strlen(buf));
close(gpiofd);
}
int gpio_read(int gpio)
{
char in[3] = {0, 0, 0};
char buf[50];
int nread, gpiofd;
sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio);
gpiofd = open(buf, O_RDWR);
if(gpiofd < 0) {
fprintf(stderr, "Failed to open gpio %d value\n", gpio);
perror("gpio failed");
}
do {
nread = read(gpiofd, in, 1);
} while (nread == 0);
if(nread == -1){
perror("GPIO Read failed");
return -1;
}
close(gpiofd);
return atoi(in);
}
int gpio_write(int gpio, unsigned char val)
{
char buf[50];
int nread, ret, gpiofd;
sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio);
gpiofd = open(buf, O_RDWR);
if(gpiofd > 0) {
snprintf(buf, 2, "%d", val);
ret = write(gpiofd, buf, 2);
if(ret < 0) {
perror("failed to set gpio");
return 1;
}
close(gpiofd);
if(ret == 2) return 0;
}
return 1;
}
int gpio_direction(int gpio, int dir)
{
int ret = 0;
char buf[50];
sprintf(buf, "/sys/class/gpio/gpio%d/direction", gpio);
int gpiofd = open(buf, O_WRONLY);
if(gpiofd < 0) {
perror("Couldn't open IRQ file");
ret = -1;
}
if(dir == 2 && gpiofd){
if (3 != write(gpiofd, "high", 3)) {
perror("Couldn't set GPIO direction to out");
ret = -2;
}
}
if(dir == 1 && gpiofd){
if (3 != write(gpiofd, "out", 3)) {
perror("Couldn't set GPIO direction to out");
ret = -3;
}
}
else if(gpiofd) {
if(2 != write(gpiofd, "in", 2)) {
perror("Couldn't set GPIO directio to in");
ret= -4;
}
}
close(gpiofd);
return ret;
}
int main(int argc, char **argv) {
int gpio_pin1 = 12,gpio_pin2=13,gpio_pin3=69,i;
struct timespec tim, tim2;
tim.tv_sec = 0;
tim.tv_nsec = 50;
gpio_export(gpio_pin1);
gpio_direction(gpio_pin1, 1);
gpio_export(gpio_pin2);
gpio_direction(gpio_pin2, 1);
gpio_export(gpio_pin3);
gpio_direction(gpio_pin3, 1);
unsigned char value=12;
while(1)
{
gpio_write(gpio_pin1,value);
gpio_write(gpio_pin2,value);
gpio_write(gpio_pin3,value);
usleep(10);
//nanosleep(&tim, NULL);
//value = value ? 0:1;
//printf("val: %d\n",value);
}
gpio_unexport(gpio_pin1);
gpio_unexport(gpio_pin2);
gpio_unexport(gpio_pin3);
return 0;
}
Thanks & Regards
Vamsi
Part Number:TMS320C6746
In table 6-57 of data sheet SPRS591F max of td(CHXH-DXV) is given as 12*P + some ns in multi channel mode.
From this I conclude that tc(CKRX) must be larger than 120 ns for P = 10ns.
Is this correct?
Part Number:TDA3
안녕하십니까.
나는 TDA3 + LPDDR2 의 Custom Board에 이미지를 작성하려고 합니다.
최종 목적은 Custom Board의 I2C 통신이 정상적으로 작동하는지 확인하기 위함입니다.
나는 Vision SDK UserGuide TDA3xx.pdf 에서 사용된 예제 파일을 수정하여 image를 빌드한 뒤, CCS 부팅을 이용하여 확인하려고 합니다.
※흐름의 요약
-----------------------------------------------------
POROCESSOR_SDK_VISION_03_04_00_00\ti_component_drivers\pdk_01_10_00_08\packages\ti\csl\example\i2c\i2c_led_blank
위 파일의 내용을 UserGuide의 예제 파일 코드에 추가합니다.
gmake를 사용하여 아래의 이미지 파일을 빌드합니다.
vision_sdk_arp32_1_release.xearp32F
vision_sdk_c66xdsp_1_release.xe66
vision_sdk_c66xdsp_2_release.xe66
vision_sdk_ipu1_0_release.xem4
vision_sdk_ipu1_1_release.xem4
해당 이미지를 CCS 부팅(UserGuide의 3.7)을 이용하여 부팅합니다.
CCS 부팅을 할 때 Scripts -> TDA3xx MULTICORE Initialization -> TDA3xx_MULTICORE_EnableCores 를 한 다음에, DDR Memory Setting -> LPDDR2 400Mhz 도 선택합니다.
다른 모든 부분은 가이드와 동일하게 진행합니다.
-----------------------------------------------------
이렇게 수행하였지만, 정상적으로 실행이 되지 않았습니다.
그래서 조금 더 찾아본 후, PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\apps\configs\tda3xx_evm_bios_all\cfg.mk 파일을 확인하였습니다.
해당 파일에는 DDR_MEM=DDR_MEM_512M 으로 되어있었고, Supported values: DDR_MEM_512M DDR_MEM_128M 으로 되어있었습니다.
이 이미지 파일을 LPDDR2 용으로 수정하려면 어떻게 해야할까요?
도움을 부탁드립니다.
(이전에 qspi 부팅과 관련하여 비슷한 질문을 하였습니다만, 완전히 별도의 문제입니다.)
Hello.
I am trying to create an image on the Custom Board of TDA3 + LPDDR2.
The final purpose is to verify that the I2C communication of the Custom Board is operating normally.
I would like to build the image by modifying the example file used in the Vision SDK UserGuide TDA3xx.pdf and check it using CCS boot.
※ Flow Summary
-------------------------------------------------- ---
PROCESSOR_SDK_VISION_03_04_00_00\ti_component_drivers\pdk_01_10_00_08\packages\ti\csl\example\i2c\i2c_led_blank
Add the contents of the this file to the example code of the UserGuide.
Use gmake to build the image file below.
vision_sdk_arp32_1_release.xearp32F
vision_sdk_c66xdsp_1_release.xe66
vision_sdk_c66xdsp_2_release.xe66
vision_sdk_ipu1_0_release.xem4
vision_sdk_ipu1_1_release.xem4
Boot the image using CCS Boot (UserGuide 3.7).
When boot CCS, select Scripts -> TDA3xx MULTICORE Initialization -> TDA3xx_MULTICORE_EnableCores, then select DDR Memory Setting -> LPDDR2 400Mhz.
All other parts are the same as the guide.
-------------------------------------------------- ---
I did this, but it did not run properly.
So I checked PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\apps\configs\tda3xx_evm_bios_all\cfg.mk file.
The file had DDR_MEM = DDR_MEM_512M and Supported values: DDR_MEM_512M DDR_MEM_128M.
How do I modify this image file for LPDDR2?
Thank you for your help.
(I've asked similar questions about booting qspi before, but this is a completely separate issue.)
Part Number:AM6548
I do not understand the SerDes sharing on the AM654x. Can USB3, Ethernet and PCIe be used simultaneously? i.e. some sort of dynamic switching?
I'm looking at Figure 12-1841 in the Technical Reference manual.
Regards,
Marc
Part Number:TDA3XEVM
Our image sensor is Vanadium Oxide(VOx) Resistive Microbolometers Infrared Thermal Detectors Focal Plane Array(FPA).
Our application is night vision. It's a hunting application. Our product is RifleScope.
FPA output is 14-bit, 640 x 480, monochrome, High Dynamic Range, it's not companded. We can select 12-bit monochrome mode in TI ISP for processing 14-bit image sensor output. Do we have any options with TI chip to process all 14 bits?
Thanks in advance.
Regards,
Amer
Part Number:AM5748
Tool/software: Linux
HI
as I can not find tidl dsp lib,but I find tidl dsp and eve library tidl_algo.lib in TDA PROCESSOR_SDK_VISION_03_06_00_00
could I use this tidl_algo.lib in AM57XX soc , and how could I use it
what is the difference between betweenTDA2 TIDL and AM57xx TIDL?
Regards,
xue
Part Number:66AK2H12
Recently,I communicate the 66AK device to other device with SGMII. I have a question about the relationship between QMSS and PKTDMA.Is there a one-to-one relationship between the QMSS queue number and the DMA channel number? For example,if we use the queue number 648 to send data,we must use the 8th DMA channel of the NETCPDMA? When I choose the queue number 647 to send data, no matter what channel of the NETCPDMA set ,no data can be sended. My test programe send as an attachment(Please visit the site to view this file)
Part Number:TCI6630K2L
In general, why are K2L datasheets and errata not getting updated ?
The Keystone II errata relevant to the K2L is not being kept up to date?
The last update to the K2L errata was in 2015. (http://www.ti.com/lit/er/sprz418b/sprz418b.pdf
I just verified that the K2L has the errata - KeyStoneII.BTS_errata_advisory.47 listed in SPRZ402F. This has taken me about 2-3 weeks to track this down and finally come across the errata in another device's errata list.
I verified this exists in the K2L and had to set the DFE_BW_SCALE to full in uboot to get around this problem.
How many more Keystone II errata from the K2H affect the K2L that aren't documented?
Additionally, there are other threads in the E2E community about discrepancies in the datasheets which TI employees have verified, but have not been updated.
This requires a lot of time searching on the customer's part and is very prone to error.
Part Number:TDA2EVM5777
Tool/software: TI-RTOS
Hi Yordon,
I am also facing this similar issue with infinite logs on running ./apps.out
I followed Sec 2.4.2.1 from VisionSDK_LinuxUserGuide.pdf and used the script <INSTALL_DIR>/vision_sdk/build./hlos/scripts/linux/setup_linux.sh
THis script has same git checkout mentioned in the Sec 2.4.2.1(See snapshot of this script)#!/bin/bash
echo " Linux Build Setup"
#setup_linux.sh
#update the sdk path
SDK_PATH=$(pwd)
CURR_DIR=$(pwd)
LINUX_TOOLS_PATH=$SDK_PATH/../../ti_components
mkdir -p $LINUX_TOOLS_PATH/os_tools/linux/kernel
cd $LINUX_TOOLS_PATH/os_tools/linux/kernel
echo "Cloning Kernel"
git clone git://git.ti.com/glsdk/infoadas-kernel.git omap
cd omap/
git checkout -b kernel_dev tags/REL_VISION_SDK_03_06_00_00
cd $CURR_DIR
echo "Cloning Cmem"
mkdir -p $LINUX_TOOLS_PATH/os_tools/linux/kernel/cmem
cd $LINUX_TOOLS_PATH/os_tools/linux/kernel/cmem
git clone git://git.ti.com/ipc/ludev.git
cd ludev/
git checkout -b cmem_dev tags/"4.14.01.00"
cd $CURR_DIR
echo "Cloning UBoot"
mkdir -p $LINUX_TOOLS_PATH/os_tools/linux/u-boot
cd $LINUX_TOOLS_PATH/os_tools/linux/u-boot
git clone git://git.ti.com/glsdk/infoadas-u-boot.git u-boot
cd u-boot/
git checkout -b uboot_dev tags/REL_VISION_SDK_03_06_00_00
cd $CURR_DIR
echo "Cloning SGX ddk"
mkdir -p $LINUX_TOOLS_PATH/os_tools/linux/sgx
cd $LINUX_TOOLS_PATH/os_tools/linux/sgx
git clone git://git.ti.com/graphics/omap5-sgx-ddk-linux.git
cd omap5-sgx-ddk-linux/
git checkout -b sgx_dev fd47e44
echo "Basic Linux Setup for 4.4 done"
echo "Download the filesystem and untar"
PLease let me know what could cause this issue ?
Thanks
Part Number:AM6548
Hello,
just a quick question: I would like to access external memory from PRU on AM6548. I found several examples how to to it with the AM35x or AM4x. On the AM3x, the OCP-Interface must be enabled to access external memory from PRU for example.
However, I found no example for AM65. The PRU seems to be connected via CBASS0 interconnect to MSMC.
So, do I need to configure the ICSSG somehow to access the DDR RAM (NAVSS0_NBSS_MSMC1_DDRLO_INT at address 0x0080000000) ? Or just create a pointer to that address to read/write? (I've tested this, it did not work however).
Do I need to configure CBASS0?
I would appreciate any hints!
Best regards,
Thomas
Part Number:TDA2PXEVM
Hello,
I am using the MCAN of TDA2PXEVM. I am trying to send 2 Tx messages at 20 msec using the transmitMsgOverMCAN function. In the same time i am receiving CAN message from the CAN bus.(CAN Bus load 30%).
Baudrate 500Kbps. After 20 to 30 Sec the System Hangs and No Tx message goes out. No errors for RX message observed in the CANoe logs. Please let me know if Tx Configuration needs to be done to resolve the System hang.
Below are the Tx and Rx Msg configuration settings.
#define MCAN_STD_ID_FILTER_NUM (15U)
#define MCAN_EXT_ID_FILTER_NUM (1U)
#define MCAN_TX_BUFF_SIZE (5U)
#define MCAN_TX_FIFO_SIZE (0U)
#define MCAN_FIFO_0_NUM (5U)
#define MCAN_FIFO_1_NUM (64U)
#define MCAN_TX_EVENT_FIFO_WATERMARK (3U)
#define MCAN_RX_FIFO_0_WATERMARK (3U)
#define MCAN_RX_FIFO_1_WATERMARK (60U)
#define MCAN_RX_FIFO_0_OPMODE (0U)
#define MCAN_RX_FIFO_1_OPMODE (0U)
#define MCAN_TX_BUFF_MODE (0U)
gMcan_msgRAMConfigParams.lss = MCAN_STD_ID_FILTER_NUM;
gMcan_msgRAMConfigParams.lse = MCAN_EXT_ID_FILTER_NUM;
gMcan_msgRAMConfigParams.txBufNum = MCAN_TX_BUFF_SIZE;
gMcan_msgRAMConfigParams.txFIFOSize = MCAN_TX_FIFO_SIZE;
gMcan_msgRAMConfigParams.txBufMode = MCAN_TX_BUFF_MODE;
gMcan_msgRAMConfigParams.txBufElemSize = MCAN_ELEM_SIZE_64BYTES;
gMcan_msgRAMConfigParams.txEventFIFOSize = MCAN_TX_BUFF_SIZE;
gMcan_msgRAMConfigParams.txEventFIFOWaterMark = MCAN_TX_EVENT_FIFO_WATERMARK;
gMcan_msgRAMConfigParams.rxFIFO0size = MCAN_FIFO_0_NUM;
gMcan_msgRAMConfigParams.rxFIFO0waterMark = MCAN_RX_FIFO_0_WATERMARK;
gMcan_msgRAMConfigParams.rxFIFO0OpMode = 0x1;
gMcan_msgRAMConfigParams.rxFIFO1size = MCAN_FIFO_1_NUM;
gMcan_msgRAMConfigParams.rxFIFO1waterMark = MCAN_RX_FIFO_1_WATERMARK;
gMcan_msgRAMConfigParams.rxFIFO1OpMode = 0x1;
Thanks and Regards,
Sanjai
Part Number:TDA2PXEVM
Hello Friends,
I have implemented Object Detection and Semantic Segmentation using TIDL and using JDetNet SSD.I find the frame rate is on the lower side.For Object Detection I am getting 8.5 fps and for Semantic Segmentation I am getting 1.5 fps.
Are there ways to improve the frame rate?
I have thought about the following methods:
• Divide the Algorithm Link into many light weight algorithm links in order to maintain the fps numbers maintained by other links in the chain.
• Choice of Deep Learning network
• Adjust the InWidth and InHeight used for the DL algorithm to achieve optimum performance
• Change the sync threshold parameters to achieve optimum performance
Please validate them and also please let me know if there are additional methods to improve output fps.(Please note that I am using TDA2P which has 2 EVE cores)
Best Regards,
Vijay
Part Number:TMS320C5533
Hi team,
I'm considering TMS320C5533 for an upcoming project that will provide bidirectional stereo USB audio to I2S connectivity and require a robust USB audio solution. I have a couple questions:
Thanks,
Brian
Part Number:DM3730
Hi everybody ,
I would like to mount 8Gb instead of 4Gb ( due to availability ) without any changes to my code and OS ( using only 4Gb out of newer memory ) .
in particular we do not want changes in muxing and as per TRM it looks like MUX16 can do this ,.
we did a first test on a board and it worked but we would like confirmation no issue can happen
is it correct what we are doing ? memory organization is the same
regards
Carlo
Part Number:TMDSLCDK138
OMAP-L138/C6748 DEV Kit LCDK layout file question:
The schematic shows that two pins, D4 and D5 of the UPP port, are not brought out to any connector.
I want to look at the layout file to see if those pins are brought out to pads that are accessible on the PC board.
Can you tell me what system generated the .brd file? Is it available in other formats or as Gerber files? We have not been able to open the attached layout file.
Part Number:TMS320C6416
Dear all,
one of my AA, is facing issues with the TMS320C6416.
The failures consists in failing the boot if the time from off to on is less than 4 seconds. Replacing the TMS320C6416 with others the issue disappeared.
I have a report that I can share by email.
regards,
Domenico
Part Number:TMS320VC5409A
If we replace PN TMS320VC549GGU-80 with PN TMS320VC5409A does the software have to be recompiled for that new part. Are the tools the same?"
Part Number:BEAGLEBK
Hello all,
I am currently working on the following project 0
dev.ti.com/.../154-stack_03_linux_project_0.html
I am working on task 3 in the above link , titled Task 3: Install the TI-15.4 Stack Linux Gateway SDK
I installed this file by following the link , ti154stack_linux_x64_2_08_00_04.run
and through the Linux terminal ( I am using Linux Mint 19) I navigated to the folder where the above file is installed , and I put the following commands in the terminal as stated per the instructions:
neil@neil-LIFEBOOK-AH531:~/Downloads$ +x ti15.4stack_linux_x64_2_08_00_04.run$./ti15.4stack_linux_x64_2_08_00_04.run
+x: command not found
neil@neil-LIFEBOOK-AH531:~/Downloads$ ti15.4stack_linux_x64_2_08_00_04.run$./ti15.4stack_linux_x64_2_08_00_04.run
bash: ti15.4stack_linux_x64_2_08_00_04.run$./ti15.4stack_linux_x64_2_08_00_04.run: No such file or directory
Any help would be appreciated. Regards.
Neil Mustafa.