Part Number:TMS320C6678
Tool/software: TI-RTOS
Is it possible to use OpenMP functions in secondary bootloader?. If yes, then I am getting errors for using openmp functions.
PS:
I have a custom secondary bootloader. I am trying to run two different application on different cores using openMP.
Part Number:TDA2P-ABZ
Tool/software: Linux
Hello TI,
I was wondering if it is possible to raise the frequency of the EVE and DSP (and possibly other cores) of the TDA2P. I have managed to raise the A15 frequency by fixing the values in the dra7.dtsi to:
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp_nom@1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1250000 950000 1250000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
Is it possible to do something similar for EVE and DSP only? Omapconf show opp command shows that they are working on 535Mhz and 850MHz , respectively. I am using PROCESSOR_SDK_VISION_03_05_00_00 with Linux.
Regards,
Stefan.
Part Number:AM6548
Hi,
We’ve tested just memory check with AM65x IDK by using SD card which was enclosed in AM65x IDK kit, then the fin became so very hot.
Let me just confirm. This fin is good enough to not over Tjmax without fan, right ? There is a connector for attaching fan on the board, but a fan was not enclosed in IDK kit. That’s OK?
Probably, we have to estimate power consumption of applications, but we can not yet get Power Estimation Tools and Thermal consideration application note.
Thanks and regards,
Hideaki Matsumoto
Part Number:AM3358
Tool/software: Linux
We have a custom board. we can power 2 ways like in beaglebone black .via USB and direct DC voltage.
Now the issue is from uboot when I probe i2c dev 1
when the board is connected on USB power I can communicate to the I2C dev on bus 1 but when I connect the board on DC power then I am unable to connect to I2C dev 1 . The I2C slave is not detected when on DC power and it gets detected when on USB.
Same is the case with Linux
Thanks,
Part Number:TDA2EVM5777
Is TDA2EVM5777 evaluation board? What SOC or processor is on this evaluation board?
Part Number:AM5726
If we move from DM50x to AM572x, what functionality do we gain? And what functionality do we lose?
DM50x has Image Signal Processor(ISP) and Display Subsystem(DSS). Does AM572x have these resources?
Part Number:AM3358
Hello,
I would like to know how to evaluate if a JTAG chain works correctly? Which methodologies might be used to evaluate it?
My JTAG chain is:
- BeagleBone Black revC (https://beagleboard.org/black)
- FTR-110-51-S-D-06 (uk.farnell.com/.../2856408)
- ARM20cTI20 – cTI 20-pin JTAG Adapter Board (www.tincantools.com/.../)
- ARM-USB-TINY-H(www.olimex.com/.../)
- OpenOCD 0.10.0 with -f interface/ftdi/olimex-arm-usb-tiny-h.cfg -f board/ti_beaglebone_black.cfg
To test it, I try to flash a baremetal binary from TI StarterWare (software-dl.ti.com/.../index_FDS.html) with OpenOCD.
This binary works well when it is launch with Uboot on a loadaddr 0x80000000.
But when I flash it across OpenOCD, it fails.
I don't understand why. I am newbie with OpenOCD. I don't understand how Openocd works. I do not know if my problem is due to a hardware incompatibility or if I apply a bad software configuration.
Could help me? Thank you in advance.
Logs:
Open On-Chip Debugger 0.10.0+dev-00567-gcea40152f (2018-11-03-20:42)
Licensed under GNU GPL v2
For bug reports, read
openocd.org/.../bugs.html
adapter speed: 1000 kHz
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain connect_deassert_srst
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1000 kHz
Info : JTAG tap: am335x.jrc tap/device found: 0x2b94402f (mfg: 0x017 (Texas Instruments), part: 0xb944, ver: 0x2)
Info : JTAG tap: am335x.tap enabled
Info : am335x.cpu: hardware has 6 breakpoints, 2 watchpoints
Info : am335x.cpu rev 2, partnum c08, arch f, variant 3, implementor 41
Error: MPIDR not in multiprocessor format
Info : Listening on port 3333 for gdb connections
Info : Listening on port 3334 for gdb connections
Info : accepting 'telnet' connection on tcp/4444
Info : JTAG tap: am335x.jrc tap/device found: 0x2b94402f (mfg: 0x017 (Texas Instruments), part: 0xb944, ver: 0x2)
Info : JTAG tap: am335x.tap enabled
Error: Debug regions are unpowered, an unexpected reset might have happened
Error: JTAG-DP STICKY ERROR
Warn : am335x.cpu: ran after reset and before halt ...
Info : am335x.cpu rev 2, partnum c08, arch f, variant 3, implementor 41
target halted in Thumb state due to debug-request, current mode: Supervisor
cpsr: 0x400001b3 pc: 0x0002412a
MMU: disabled, D-Cache: disabled, I-Cache: disabled
Error: data abort at 0x80000000, dfsr = 0x00001808
init
reset init
halt
load_image /srv/tftp/uartEcho_ti.bin 0x80000000 bin
resume 0x80000000
I don't understand also, why after each reset:
- the CPU is in Thumb state?
- when I am in GDB interface the CPU target is am335x.m3 (cortex_m, Trust Zone, isn't it?) and when I am in telnet interface the CPU target is
am335x.cpu (cortex_a)?
Part Number:SITARA-DDR-CONFIG-TOOL
Tool/software: TI-RTOS
HEY! Why doesn't this site let you PASTE IN CODE??
How completely USELESS is an "E2E" Site, if you YOU CAN'T EVEN PASTE SAMPLE CODE??
All it does is ERASE THE BIG LONG REPLY I TYPED, so ALL your work IS GONE. YES GONE!!!
Then it pops up a message that says AN ERROR OCCURRED, TRY AGAIN. Gee... thanks.
And there is NO PLACE to actually tell anyone that THIS FORUM web site is DEFECTIVE.
Does anyone at TI ever TEST this stuff???
I had to pick a RANDOM device, in order to get to be able to complain... In the (lost cause) that I can get through to someone who admins this thing.
Part Number:TMDSLCDK6748
Tool/software: TI-RTOS
I am using the latest version of CCS and SDK and all other packages.
I have configured the onboard codec AIC3106 in master mode and configured its sampling rate to be 48kHz when I record the data and plot it in Matlab, the sampling rate happens to 62640Hz. After searching the forum, I came through this post and did the changes but still the sampling rate is 47990Hz instead of 48kHz. (I got this result by taking FFT of 1-second samples )
What is the problem here? How do I get 48kHz and also is it possible to have a 96kHz sampling rate while using both the channels, How? can you provide code for that?
MY CODE:
unsigned char temp;
unsigned char fsDivVal;
unsigned char nVal;
unsigned char mVal = 8;
unsigned short osrVal = 128;
unsigned char ref = 0x0A;
// unsigned char pllPval = 1;
unsigned char pllPval = 2;
unsigned char pllRval = 1;
pllJval = 8u;
pllDval = 0u;
fsDivVal = 1;
Part Number:AM6548
Tool/software: Linux
Hello,
I see that the latest Linux SDK release has ECC support disabled in the AM654x DDR4 configuration dtsi file even though it is offered as an option in the EMIF configuration spreadsheet and is populated on the hardware. Has ECC support been tested and/or verified for the AM6548 processor?
Thanks,
Matt McKee
Part Number:TMS320C6748
Tool/software: Code Composer Studio
I am using shared RAM between PRU0 and Host. And, I am using CCS 8.2 for debugging. As you know, debugging PRU code is a bit cumbersome as PRU is not conveniently controllable. The specific problem I'm encountering is that PRU is able to read from shared RAM but unable to write, it seems. Host can read and write.
To illustrate the problem a bit more, PRU handles SPI communication. It passes data between a peripheral device connected to SPI0 and host via the shared RAM. When it receives data, it writes it shared RAM and host picks it up later as needed.
Is there a control register setting I'm missing?
Part Number:TMS320C6472
I have a customer trying to manually test the HPI interface on the TI TMS320C6472ECTZA6 DSP. Is there a sequence of writes and reads one can use to verify the HPI operation?
Customer can read back the HPIC and HPIA register value, but any location they have attempted to read returns 00000000.
My sequence is:
mw.w 60000000 0003
mw.w 60000000 0000 Resets DSPs
mw.w 40000000 0001
mw.w 40000002 0001 Sets HPIC for LSW first mw.w 40000004 0000 mw.w 40000006 0020 Sets access to register 0x00200000 mw.w 4000000C 1234 mw.w 4000000E 5678 Writes Data
mw.w 40000000 0000
mw.w 40000002 0001 Sets HPIC for LSW first mw.w 40000004 0000 mw.w 40000006 0020 Sets access to register 0x00200000 md.w 4000000C md.w 4000000E Reads Data
Part Number:AM4376
Tool/software: Linux
We have incorporated a Micron MT25QU01 128MB QSPI Flash part into our hardware design that contains a AM4376 Processor. The QSPI Flash part support the QUAD INPUT FAST PROGRAM in either 1-1-4 or 4-4-4 mode. Looking at the QSPI controller it mentions support for quad reads but doesn't mention anything about support quad writes. Is this something that is possible with the TI QSPI controller on the AM4376? Or are we limited to just using a serial flash write (single SPI)?
Thanks,
-Ryan
Part Number:TDA2
In TDA2x Superset, can H.264 encoding achievable purely in hardware using IVA HD Co-Processor?
Regards,
Amer
Part Number:PROCESSOR-SDK-AM335X
Tool/software: Linux
Hi,
I created a bootable SD card using the create-sd-card.sh script that ships with the TI SDK 05.00.00.02. I'm able to boot from the SD card through the usual method of holding the S1 button.
I also have a working image at the eMMC that I'd like to keep. I don't want to erase it or to flash the SD card contents into the eMMC.
So, how could I boot from the SD card without pressing the S1 button? Currently, I don't have any uEnv.txt file in the boot partition of the SD card.
Regards,
Bruno.
