Part Number:AM5708

Tool/software: Linux

How do I set Weston to use RGB888 (not xrgb888, not rgb565) on AM5708?

If I set it to "rgb888" via /etc/weston.ini, Weston does not come up:

[18:37:19.166] weston 2.0.0
http://wayland.freedesktop.org
Bug reports to: bugs.freedesktop.org/enter_bug.cgi
Build: 5b55db0-dirty JOME Weston Controller Change 2 (2018-10-25 14:53:08 +0000)
[18:37:19.166] Command line: weston --idle-time=0
[18:37:19.166] OS: Linux, 4.14.54-g976d7a5851, #1 SMP PREEMPT Thu Jan 3 15:57:42 UTC 2019, armv7l
[18:37:19.167] Using config file '/etc//weston.ini'
[18:37:19.174] Output repaint window is 7 ms maximum.
[18:37:19.176] Loading module '/usr/lib/libweston-2/drm-backend.so'
[18:37:19.188] initializing drm backend
[18:37:19.188] fatal: unrecognized pixel format: rgb888

Part Number:AM5728

Tool/software: Linux

Hi,

I have done the following to enable the uart ports:

- Decompile /boot/dtbs/4.14.79-ti-r84.1/am57xx-beagle-x15-revc.dtb into a .dts

- Edit the status field to "okay" of the following ports:

serial@4806a000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4806a000 0x100>;
   interrupts-extended = <0x1 0x0 0x43 0x4>;
   ti,hwmods = "uart1";
   clock-frequency = <0x2dc6c00>;
   status = "okay";
   dmas = <0xb3 0x31 0xb3 0x32>;
   dma-names = "tx", "rx";
   phandle = <0x1a7>;
  };

  serial@4806c000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4806c000 0x100>;
   interrupts = <0x0 0x44 0x4>;
   ti,hwmods = "uart2";
   clock-frequency = <0x2dc6c00>;
   status = "okay";
   dmas = <0xb3 0x33 0xb3 0x34>;
   dma-names = "tx", "rx";
   phandle = <0x1a8>;
  };

- Recompile the dts to dtb.

Now I can see how uart 0 and 1 have a ttyO0 and ttyO1 in /dev/ and the following information is shown when I run cat /proc/tty/driver/serial:

0: uart:8250 mmio:0x4806A000 irq:45 tx:0 rx:0 DSR                               
1: uart:8250 mmio:0x4806C000 irq:46 tx:0 rx:0 DSR                               
2: uart:8250 mmio:0x48020000 irq:47 tx:193 rx:0 RTS|DTR|DSR                     
3: uart:unknown port:00000000 irq:0                                             
4: uart:unknown port:00000000 irq:0                                             
5: uart:unknown port:00000000 irq:0                                             

However, if we probe the pins corresponding to those uart we don't see data going through when it is sent.

What else do we need to do to enable UARTs ?

Thank you.

Part Number:DM385

Hello,

My customer is asking the following question about DM385– can you please assist?

What is the “maximum one time force and life time force that can be applied to T.I. P/N DM385AAAR21?” 

Do we have some sort of pressure spec for this device?

Thanks,

Vikrum

Part Number:TMS320C6678

When using the dev. board it is usual to first run a gel file, evmc6678l.gel, to initialise parts of the device, e.g.DDR3.

Then a large-scale program (.out) file that uses DD3 can be loaded and run.

What is the recommended method to package such a program  so that it can be booted onto the board over internet,

in a stand-alone way, without having to run the gel script ?

Presumably, a boot parameter table and DDR3 configuration table have to be incorporated into the boot image?

How is this achieved?

Part Number:66AK2H14

Hello, I'm designing a board with the 66AK2H14 processor with two DDR3 banks at 1.35V. I'm planning on using a 0.675V Termination Regulator (TPS51200MDRCTEP) for both DDR banks. Is it okay to share the regulator on both DDR banks?

Thanks,

Joe

Part Number:AM5728

Champs,

Customer would like to follow the tracks of the DDR configuration spreasheet for TI IDK EVM. The spreadsheet available for download on TI.com says it is for "TI_AM574x_EVM" which is not quite clear whether it is the AM5748 IDK or AM5728/48 GP EVM.

In any case -- would it be possible to get the spreadsheet filled out for the AM5728 IDK?

thanks

Michael

Part Number:66AK2G12

Tool/software: TI-RTOS

Customer Question:

"

We have the following configuration:

K2G12 processor with DDR3L SDRAM

Both ARM and DSP under TI-RTOS with the following versions

bios_6_46_05_55

CCS Version: 7.2.0.00013

pdk_k2g_1_0_7

processor_sdk_rtos_k2g_4_01_00_06

We would like to declare K2G MSMC to be non-cacheable for both ARM and DSP. The address of MSMC starts from 0x0c000000. The size is 1MB.

We are able to declare K2G MSMC to be non-cacheable from ARM perspective but not DSP.

Refer to the link below

https://e2e.ti.com/support/processors/f/791/t/718619?tisearch=e2e-quicksearch&keymatch=disable cache MSMC

We disable cache on DSP in .cfg file like below:

var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');

// Cache.setMarMeta(base_address, length, Cache.Mar_DISABLE)

Cache.setMarMeta(0x0C000000, 0x00100000, Cache.Mar_DISABLE);

But we still need to call CacheP_wbInv() in order to update DSP data correctly.

How to declare K2G MSMC to be non-cacheable from  DSP perspective?"

Tool/software: TI-RTOS

Maximum data throughput AM572x can support?  Assumed to use  one A15 core and one C66xx DSP core in the Dev Board. 

Part Number:TMS320C5535

Using the examples from the CSL support library, I've tried to set up a GPT interrupt that blinks an LED on and off so that I can get familiar with the processor. However, I can't seem to set it up correctly because the program never enters the ISR. To help with the debugging, I initialized a flag and am trying to toggle the flag in the ISR at a rate of 1 second using a GPT with a system clock of 100Mhz. 

My code is as follows: 

#include <stdio.h>
#include <stdint.h>
#include <csl_general.h>
#include "csl_sysctrl.h"
#include "csl_gpio.h"
#include "csl_intc.h"
#include "csl_gpt.h"
#include "csl_pll.h"
#include "csl_pllAux.h"

/////////////* Preprocessor Directives */////////////
#define CSL_TEST_FAILED    (1u)
#define CSL_TEST_PASSED    (0)
#define CSL_PLL_CLOCKIN    (32768u)

/////////////* Function Forward Declarations */////////////
int EBSR_init(void);
int GPIO_init(void);
int GPT_init(void);

/////////////* Global Variables */////////////
Uint32 sysClk = 0;
Uint16 readLED1_Val;
Uint16 readLED2_Val;

/////////////* Global Structs and Objects */////////////
CSL_GpioObj gpioObj;
CSL_GpioObj *hGpio;

PLL_Obj pllObj;
PLL_Obj *hPll;

PLL_Config pllCfg1;
PLL_Config *pConfigInfo;

PLL_Config pllCfg_100MHz = { 0x8BE8, 0x8000, 0x0806, 0x0000 };

/////////////* Volatile Variables */////////////
extern void VECSTART(void);
interrupt void blinkLED(void);
volatile Bool flag = 0;

Uint32 ctrVal = 0;
CSL_Handle hGpt;

/////////////* Main Function */////////////
int main(void)
{
    /////////////* Initializations */////////////
    int result;

    PLL_init(&pllObj, CSL_PLL_INST_0);
    hPll = (PLL_Handle) (&pllObj);

    PLL_reset(hPll);

    /* Configure the PLL for 100MHz */
    pConfigInfo = &pllCfg_100MHz;
    PLL_config(hPll, pConfigInfo);

    result = EBSR_init();
    result = GPIO_init();
    result = GPT_init();


    while (result != CSL_SOK)
    {
    }; // Catches errors
    /////////////* Infinite Loop */////////////
    while (1){
        GPT_getCnt( hGpt, &ctrVal);
    }
}

/////////////* Function Definitions */////////////
int EBSR_init(void)
{
    CSL_Status status;

    status = SYS_setEBSR(CSL_EBSR_FIELD_PPMODE, CSL_EBSR_PPMODE_1);
    status |= SYS_setEBSR(CSL_EBSR_FIELD_SP1MODE, CSL_EBSR_SP1MODE_1);
    status |= SYS_setEBSR(CSL_EBSR_FIELD_SP0MODE, CSL_EBSR_SP0MODE_1);

    if (status != CSL_SOK)
    {
        return (CSL_TEST_FAILED);
    }

    return status;

}

int GPIO_init()
{
    CSL_Status status;
    CSL_GpioConfig config;

    /* Open GPIO Module */
    hGpio = GPIO_open(&gpioObj, &status);

    if (hGpio == NULL || status != CSL_SOK)
    {
        return (CSL_TEST_FAILED);
    }

    GPIO_reset(hGpio); // Resets all pins to default values

    /* Configure GPIO module */
    config.GPIODIRL = 0x9420;
    config.GPIODIRH = 0x0002;
    config.GPIOINTTRIGL = 0x0010;
    config.GPIOINTTRIGH = 0x0000;
    config.GPIOINTENAL = 0x4810;
    config.GPIOINTENAH = 0x0001;

    status = GPIO_config(hGpio, &config);

    /* Config PDINHIBRn regs */
    ioport volatile CSL_SysRegs *sysRegs;
    sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;
    sysRegs->PDINHIBR1 = CSL_SYS_PDINHIBR1_RESETVAL;                                                // Config PDINHIBR1
    CSL_FINS(sysRegs->PDINHIBR2, SYS_PDINHIBR2_INT0PU, CSL_SYS_PDINHIBR2_INT0PU_ENABLE);            // Config PDINHIBR2
//    sysRegs->PDINHIBR3 =


    if (status != CSL_SOK)
    {
        return (CSL_TEST_FAILED);
    }

    else
        return CSL_TEST_PASSED;
}

int GPT_init(void)
{
    CSL_Status status;
    CSL_Config hwConfig;
    CSL_GptObj gptObj;

    /* Get the System clock value at which CPU is currently running */
    sysClk = getSysClk();

    /* Open the CSL GPT module */
    hGpt = GPT_open(GPT_0, &gptObj, &status);

    /* Reset the GPT module */
    status = GPT_reset(hGpt);

    // Initialize ISRs
    /* Disable CPU interrupt */
    IRQ_globalDisable();

    /* Clear any pending interrupts */
    IRQ_clearAll();

//    /* Disable all the interrupts */
//    IRQ_disableAll();

    /* Initialize Interrupt Vector table */
    IRQ_setVecs((Uint32) (&VECSTART));
//
//    /* Clear any pending Interrupt */
//    IRQ_clear(TINT_EVENT);

    IRQ_plug(TINT_EVENT, &blinkLED);

    /* Enabling Interrupt */
    IRQ_enable(TINT_EVENT);

    hwConfig.autoLoad = GPT_AUTO_ENABLE;
    hwConfig.ctrlTim = GPT_TIMER_ENABLE;
    hwConfig.preScaleDiv = GPT_PRE_SC_DIV_1;// 100Mhz/4 = 25Mhz
    hwConfig.prdLow = (sysClk)/4;           // Period 250,000 ticks
    hwConfig.prdHigh = 0x0000;              // So 1 second interval

    /* Configure the GPT module */
    status = GPT_config(hGpt, &hwConfig);

    IRQ_globalEnable();
    /* Start the Timer */
    GPT_start(hGpt);

    GPT_getCnt(hGpt, &ctrVal);

    return status;

}

interrupt void blinkLED(void)
{
    IRQ_clear(TINT_EVENT);
    CSL_SYSCTRL_REGS->TIAFR = 0x01;
    if (flag == 0){ flag = 1;}
    if (flag == 1){ flag = 0;}


//    GPIO_read(hGpio, CSL_GPIO_PIN15, &readLED1_Val);
//    if ( readLED1_Val == 1 )
//    {
//        GPIO_write(hGpio, CSL_GPIO_PIN15, 0);
//    }
//
//    else GPIO_write(hGpio, CSL_GPIO_PIN15, 1);
//
//    GPIO_read(hGpio, CSL_GPIO_PIN12, &readLED2_Val);
//    if ( readLED2_Val == 0 )
//    {
//        GPIO_write(hGpio, CSL_GPIO_PIN12, 0);
//    }
//
//    else GPIO_write(hGpio, CSL_GPIO_PIN12, 1);

}


Any guidance or advice would be greatly appreciated! 

Part Number:TMDSEVM6678

Tool/software: TI-RTOS

Hi, I would like to integrate a UART and Multicore IPC example, however I get an interrupt conflict (#5) at runtime between the two.  I do not know how to remap the IPC interrupt or the UART driver interrupt to point to another HWI number.

I tried the code supplied on thread:

https://e2e.ti.com/support/processors/f/791/p/187011/849689#849689 

However cannot get it to work. Compiler says that CSL_GEM_IPC_LOCAL and DEVICE_REG32_W are undefined..

Thanks for any help.

Part Number:AM3352

Tool/software: Linux

am335x board works, but there are some warning info at boot time:

...

am335x-evm daemon.warn systemd-udevd[940]: Process '/sbin/modprobe i2c:pcf8563' failed with exit code 1.

am335x-evm daemon.warn systemd-udevd[875]: Process '/sbin/modprobe platform:alarmtimer' failed with exit code 1.
 am335x-evm daemon.warn systemd-udevd[876]: Process '/sbin/modprobe platform:cpufreq-dt' failed with exit code 1.
am335x-evm daemon.warn systemd-udevd[862]: Process '/sbin/modprobe of:Ngpio-keysT<NULL>Cgpio-keys' failed with exit code 1.
am335x-evm daemon.warn systemd-udevd[867]: Process '/sbin/modprobe platform:Fixed MDIO bus' failed with exit code 1.
am335x-evm daemon.warn systemd-udevd[865]: Process '/sbin/modprobe of:Nfixedregulator0T<NULL>Cregulator-fixed' failed with exit code .
am335x-evm daemon.warn systemd-udevd[902]: Process '/sbin/modprobe of:Nfixed-regulatorT<NULL>Cregulator-fixed' failed with exit code .
am335x-evm daemon.warn systemd-udevd[939]: Process '/sbin/modprobe of:Ngpio-ledsT<NULL>Cgpio-leds' failed with exit code 1.

am335x-evm daemon.warn systemd-udevd[940]: Process '/sbin/modprobe of:NocpT<NULL>Csimple-bus' failed with exit code 1.
am335x-evm daemon.warn systemd-udevd[862]: Process '/sbin/modprobe input:b0019v0001p0001e0100-e0,1,k9E,ramlsfw' failed with exit code.

am335x-evm daemon.warn systemd-udevd[902]: Process '/sbin/modprobe of:NocmcramT<NULL>Cmmio-sram' failed with exit code 1.
am335x-evm daemon.warn systemd-udevd[876]: Process '/sbin/modprobe of:NgpioT<NULL>Cti,omap4-gpio' failed with exit code 1.
am335x-evm daemon.warn systemd-udevd[939]: Process '/sbin/modprobe of:NrtcT<NULL>Cti,am3352-rtcCti,da830-rtc' failed with exit code 1.
am335x-evm daemon.warn systemd-udevd[865]: Process '/sbin/modprobe of:NserialT<NULL>Cti,am3352-uartCti,omap3-uart' failed with exit c.
am335x-evm daemon.warn systemd-udevd[867]: Process '/sbin/modprobe of:NserialT<NULL>Cti,am3352-uartCti,omap3-uart' failed with exit c.
am335x-evm daemon.warn systemd-udevd[875]: Process '/sbin/modprobe of:NserialT<NULL>Cti,am3352-uartCti,omap3-uart' failed with exit c.

...

what should be done with dts or udevd to eliminate these warnings?

thanks

Part Number:TDA3

Tool/software: TI-RTOS

Hi, experts,

I followed the steps of  VisionSDK_UserGuide_NetworkTools.pdf, and remove FATFS, and enable the NDK. When I boot from the QSPI, I could find the EVM IP is 0.0.0.0 (DHCPC is enbled)

the log as Below:

*****************************************************************

 Jumping to IPU1 CPU1 App 

 Jumping to IPU1 CPU0 App 
[IPU1-0]      0.877569 s:  ***** IPU1_0 Firmware build time 19:08:44 Jan  2 2019
[IPU1-0]      0.877722 s:  *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz>
[IPU1-0]      1.347709 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[IPU1-0]      1.347861 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[IPU1-0]      1.347983 s:  SYSTEM: Notify register to [DSP2] line 0, event 15... 
[IPU1-0]      1.348105 s:  SYSTEM: Notify register to [EVE1] line 0, event 15... 
[IPU1-0]      1.348349 s:  *** UTILS: CPU MHz = 20 Mhz ***
[IPU1-0]      1.348471 s:  SYSTEM: System Common Init in progress !!!
[IPU1-0]      1.357683 s:  UTILS: CIO: Init Done !!!
[IPU1-0]      1.357774 s:  SYSTEM: IPC init in progress !!!
[IPU1-0]      1.357866 s:  SYSTEM: Notify init done !!!
[IPU1-0]      1.358049 s:  SYSTEM: MsgQ init done !!!
[IPU1-0]      1.358110 s:  SYSTEM: IPC init DONE !!!
[IPU1-0]      1.360306 s:  SYSTEM: System Common Init Done !!!
[IPU1-0]      1.360367 s:  SYSTEM: System Init in progress !!!
[IPU1-0]      1.360428 s:  SYSTEM: BSP Common Init in progress !!!
[IPU1-0]      1.360519 s:  SYSTEM: BSP Common Init Done !!!
[IPU1-0]      1.360611 s:  SYSTEM: BSP Platform Init in progress !!!
[IPU1-0]      1.360733 s:  SYSTEM: BSP Platform Init Done !!!
[IPU1-0]      1.360794 s:  SYSTEM: FVID2 Init in progress !!!
[IPU1-0]      1.360946 s:  SYSTEM: FVID2 Init Done !!!
[IPU1-0]      1.361038 s:  SYSTEM: VPS Init in progress !!!
[IPU1-0]      1.361099 s:  SYSTEM: VPDMA Descriptor Memory Address translation ENABLED [0xa0000000 -> 0x80000000]
[IPU1-0]      1.363661 s: *** VPDMA Firmware Loading... ***
[IPU1-0]      1.363752 s: VPDMA Firmware Address = 0x9ffc7800
[IPU1-0]      1.363844 s: VPDMA Load Address     = 0x4897d004
[IPU1-0]      1.363966 s: VPDMA Firmware Version = 0x4d0001b8
[IPU1-0]      1.364057 s: VPDMA List Busy Status = 0x00000000
[IPU1-0]      1.364149 s: *** VPDMA Firmware Load Success ***
[IPU1-0]      1.400140 s:  SYSTEM: VPS Init Done !!!
[IPU1-0]      1.400902 s:  UTILS: DMA: HWI Create for INT34 !!!
[IPU1-0]      1.401177 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[IPU1-0]      1.401268 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 257272 B (251 KB)
[IPU1-0]      1.401451 s:  SYSTEM: Heap = SR_OCMC              @ 0x00000000, Total size = 0 B (0 KB), Free size = 0 B (0 KB)
[IPU1-0]      1.401665 s:  SYSTEM: Heap = SR_DDR_CACHED        @ 0x85703000, Total size = 369086464 B (351 MB), Free size = 369086464 B (351 MB)
[IPU1-0]      1.401878 s:  SYSTEM: Heap = SR_DDR_NON_CACHED    @ 0xbfe00000, Total size = 915712 B (0 MB), Free size = 908032 B (0 MB)
[IPU1-0]      1.402061 s:  SYSTEM: Initializing Links !!! 
[IPU1-0]      1.481577 s:  SYSTEM: Initializing Links ... DONE !!! 
[IPU1-0]      1.504880 s:  BOARD: Board Init in progress !!!
[IPU1-0]      1.505215 s:  BOARD: Board Init Done !!!
[IPU1-0]      1.511041 s: Initializing Multi-Deserializer Setup ...!!
[IPU1-0]      1.511132 s:  MultiDes Board Init Done
[IPU1-0]      1.511163 s: 
[IPU1-0]      1.511193 s:  Vision SDK Version    : [REL_VISION_SDK_03_05_00_00]
[IPU1-0]      1.511285 s:  FVID2 Version         : [FVID_02_01_00_01]
[IPU1-0]      1.511346 s:  BSP Version           : [PDK_01_10_01_xx]
[IPU1-0]      1.511407 s:  Platform              : [EVM]
[IPU1-0]      1.511468 s:  SOC                   : [TDA3XX]
[IPU1-0]      1.511559 s:  SOC Revision          : [ES1.0]
[IPU1-0]      1.511651 s:  Board Detected        : [MULTIDES]
[IPU1-0]      1.518788 s:  EEPROM Base Board Name: [ADAS-LOW]
[IPU1-0]      1.518849 s:  Base Board Revision   : [REV C]
[IPU1-0]      1.518910 s:  Daughter Card Revision: [REV A]
[IPU1-0]      1.518971 s:  
[IPU1-0]      1.521594 s:  SYSTEM: UART: INTERRUPT Mode is Selected 
[IPU1-1]      0.889007 s:  ***** IPU1_1 Firmware build time 19:06:51 Jan  2 2019
[IPU1-1]      0.889160 s:  *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz>
[IPU1-1]      1.348746 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[IPU1-1]      1.348929 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[IPU1-1]      1.349020 s:  SYSTEM: Notify register to [DSP2] line 0, event 15... 
[IPU1-1]      1.349142 s:  SYSTEM: Notify register to [EVE1] line 0, event 15... 
[IPU1-1]      1.355761 s:  SYSTEM: System Common Init in progress !!!
[IPU1-1]      1.356737 s:  UTILS: CIO: Init Done !!!
[IPU1-1]      1.356829 s:  SYSTEM: IPC init in progress !!!
[IPU1-1]      1.356890 s:  SYSTEM: Notify init done !!!
[IPU1-1]      1.357073 s:  SYSTEM: MsgQ init done !!!
[IPU1-1]      1.357134 s:  SYSTEM: IPC init DONE !!!
[IPU1-1]      1.359238 s:  SYSTEM: System Common Init Done !!!
[IPU1-1]      1.359330 s:  SYSTEM: System IPU1_1 Init in progress !!!
[IPU1-1]      1.360062 s:  UTILS: DMA: HWI Create for INT25 !!!
[IPU1-1]      1.360245 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[IPU1-1]      1.360367 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 232112 B (226 KB)
[IPU1-1]      1.360550 s:  SYSTEM: Initializing Links !!! 
[IPU1-1]      1.403861 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC1 ####
[IPU1-1]      1.405325 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC2 ####
[IPU1-1]      1.406972 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC3 ####
[IPU1-1]      1.408467 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM0 ####
[IPU1-1]      1.410083 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM1 ####
[IPU1-1]      1.411730 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM2 ####
[IPU1-1]      1.413530 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM3 ####
[IPU1-1]      1.415329 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM4 ####
[IPU1-1]      1.417220 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM5 ####
[IPU1-1]      1.419172 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM6 ####
[IPU1-1]      1.421155 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM7 ####
[IPU1-1]      1.421277 s:  SYSTEM: Initializing Links ... DONE !!! 
[IPU1-1]      1.421826 s:  SYSTEM: System IPU1_1 Init Done !!!
[IPU1-1]      1.650796 s:  NSP GMAC: PHY 0 Found on MAC Port 0
[DSP1  ]      0.898371 s:  ***** DSP1 Firmware build time 19:07:17 Jan  2 2019
[DSP1  ]      0.898462 s:  *** SYSTEM: CPU Frequency <ORG = 500000000 Hz>, <NEW = 500000000 Hz>
[DSP1  ]      1.349508 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[DSP1  ]      1.349569 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[DSP1  ]      1.349630 s:  SYSTEM: Notify register to [DSP2] line 0, event 15... 
[DSP1  ]      1.349661 s:  SYSTEM: Notify register to [EVE1] line 0, event 15... 
[DSP1  ]      1.349752 s:  *** UTILS: CPU MHz = 20 Mhz ***
[DSP1  ]      1.349813 s:  SYSTEM: System Common Init in progress !!!
[DSP1  ]      1.349996 s:  UTILS: CIO: Init Done !!!
[DSP1  ]      1.350027 s:  SYSTEM: IPC init in progress !!!
[DSP1  ]      1.350057 s:  SYSTEM: Notify init done !!!
[DSP1  ]      1.350118 s:  SYSTEM: MsgQ init done !!!
[DSP1  ]      1.350149 s:  SYSTEM: IPC init DONE !!!
[DSP1  ]      1.350881 s:  SYSTEM: System Common Init Done !!!
[DSP1  ]      1.350911 s:  SYSTEM: System DSP Init in progress !!!
[DSP1  ]      1.351094 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[DSP1  ]      1.351125 s:  SYSTEM: Heap = LOCAL_L2             @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)
[DSP1  ]      1.351186 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 524288 B (512 KB), Free size = 519608 B (507 KB)
[DSP1  ]      1.351247 s:  SYSTEM: Initializing Links !!! 
[DSP1  ]      1.357744 s:  SYSTEM: Initializing Links ... DONE !!! 
[DSP1  ]      1.357805 s: lz4CompDecomp Init
[DSP1  ]      1.357805 s:  SYSTEM: System DSP Init Done !!!
[DSP1  ]      1.489599 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after boot !!!
[DSP1  ]      1.489629 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after update by APP !!!
[DSP2  ]      0.898462 s:  ***** DSP2 Firmware build time 19:07:18 Jan  2 2019
[DSP2  ]      0.898523 s:  *** SYSTEM: CPU Frequency <ORG = 500000000 Hz>, <NEW = 500000000 Hz>
[DSP2  ]      1.350332 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[DSP2  ]      1.350393 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[DSP2  ]      1.350454 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[DSP2  ]      1.350484 s:  SYSTEM: Notify register to [EVE1] line 0, event 15... 
[DSP2  ]      1.350576 s:  *** UTILS: CPU MHz = 20 Mhz ***
[DSP2  ]      1.350637 s:  SYSTEM: System Common Init in progress !!!
[DSP2  ]      1.350820 s:  UTILS: CIO: Init Done !!!
[DSP2  ]      1.350850 s:  SYSTEM: IPC init in progress !!!
[DSP2  ]      1.350881 s:  SYSTEM: Notify init done !!!
[DSP2  ]      1.350942 s:  SYSTEM: MsgQ init done !!!
[DSP2  ]      1.350972 s:  SYSTEM: IPC init DONE !!!
[DSP2  ]      1.351735 s:  SYSTEM: System Common Init Done !!!
[DSP2  ]      1.351765 s:  SYSTEM: System DSP Init in progress !!!
[DSP2  ]      1.351949 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[DSP2  ]      1.352010 s:  SYSTEM: Heap = LOCAL_L2             @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)
[DSP2  ]      1.352071 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 524288 B (512 KB), Free size = 519608 B (507 KB)
[DSP2  ]      1.352101 s:  SYSTEM: Initializing Links !!! 
[DSP2  ]      1.358659 s:  SYSTEM: Initializing Links ... DONE !!! 
[DSP2  ]      1.358689 s: lz4CompDecomp Init
[DSP2  ]      1.358720 s:  SYSTEM: System DSP Init Done !!!
[DSP2  ]      1.491581 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after boot !!!
[DSP2  ]      1.491642 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after update by APP !!!
[EVE1  ]      1.343744 s:  ***** EVE1 Firmware build time 19:06:28 Jan  2 2019 
[EVE1  ]      1.344964 s:  *** SYSTEM: CPU Frequency <ORG = 250000000 Hz>, <NEW = 250000000 Hz>
[EVE1  ]      1.350362 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[EVE1  ]      1.351369 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[EVE1  ]      1.352498 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[EVE1  ]      1.353535 s:  SYSTEM: Notify register to [DSP2] line 0, event 15... 
[EVE1  ]      1.354846 s:  SYSTEM: System Common Init in progress !!!
[EVE1  ]      1.356615 s:  UTILS: CIO: Init Done !!!
[EVE1  ]      1.357317 s:  SYSTEM: IPC init in progress !!!
[EVE1  ]      1.358049 s:  SYSTEM: Notify init done !!!
[EVE1  ]      1.359025 s:  SYSTEM: MsgQ init done !!!
[EVE1  ]      1.359665 s:  SYSTEM: IPC init DONE !!!
[EVE1  ]      1.369913 s:  SYSTEM: System Common Init Done !!!
[EVE1  ]      1.370615 s:  SYSTEM: System EVE Init in progress !!!
[EVE1  ]      1.371683 s:  UTILS: DMA: HWI Create for INT8 !!!
[EVE1  ]      1.372537 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[EVE1  ]      1.373482 s:  SYSTEM: Heap = LOCAL_L2             @ 0x40020000, Total size = 22528 B (22 KB), Free size = 22528 B (22 KB)
[EVE1  ]      1.375282 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 257432 B (251 KB)
[EVE1  ]      1.376929 s:  SYSTEM: Initializing Links !!! 
[EVE1  ]      1.445495 s:  SYSTEM: Initializing Links ... DONE !!! 
[EVE1  ]      1.446257 s:  SYSTEM: System EVE Init Done !!!
[IPU1-0]      2.525071 s:  QSPI Init Started 
[IPU1-0]      2.525315 s:  MID - 1 
[IPU1-0]      2.525376 s:  DID - 18 
[IPU1-0]      2.525407 s:  QSPI Init Completed Sucessfully 
[IPU1-0]      2.533245 s:  UTILS: DMM: API NOT supported in TDA3xx !!! 
[IPU1-0]      2.533337 s:  UTILS: DMM: API NOT supported in TDA3xx !!! 
[IPU1-0]      2.534496 s:  
[IPU1-0]      2.534587 s:  Current System Settings,
[IPU1-0]      2.534648 s:  ========================
[IPU1-0]      2.534709 s:  Display Type   : HDMI 1920x1080 @ 60fps 
[IPU1-0]      2.534770 s:  Capture Source : Sensor OV10635 1280x720  @ 30fps - VIP, YUV422 
[IPU1-0]      2.534831 s:  My IP address  : 0.0.0.0 
[IPU1-0]      2.534892 s:  ISS Settings   : LDC=[OFF] VTNF=[OFF] WDR=[OFF] 
[IPU1-0]      2.534984 s:  
[IPU1-0]      2.535014 s:  ============
[IPU1-0]      2.535045 s:  Usecase Menu
[IPU1-0]      2.535106 s:  ============
[IPU1-0]      2.535136 s: 
[IPU1-0]  
[IPU1-0]  Vision SDK Usecases,
[IPU1-0]  -------------------- 
[IPU1-0]  1: Single Camera Usecases
[IPU1-0]  2: Multi-Camera LVDS Usecases
[IPU1-0]  3: AVB RX Usecases, (TDA2x & TDA2Ex ONLY)
[IPU1-0]  4: Dual Display Usecases, (TDA2x EVM ONLY)
[IPU1-0]  5: ISS Usecases, (TDA3x ONLY)
[IPU1-0]  6: TDA2x Stereo Usecases 
[IPU1-0]  9: RADAR Usecases
[IPU1-0]  a: Miscellaneous test's
[IPU1-0]  f: TIDL Usecase
[IPU1-0]  g: Camera Radar Combo Usecases
[IPU1-0]  
[IPU1-0]  s: System Settings 
[IPU1-0]  
[IPU1-0]  x: Exit 
[IPU1-0]  
[IPU1-0]  Enter Choice: 
[IPU1-0]  
[IPU1-1]      6.421673 s:  NETWORK_CTRL: Starting Server (port=5000) !!!
[IPU1-1]      6.421765 s:  NETWORK_CTRL: Starting Server ... DONE (port=5000) !!!
[IPU1-1]     27.152168 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]     27.351674 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]     62.853108 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]     63.152687 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]     97.854084 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]     98.053589 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]    127.254864 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]    127.454370 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]    164.755871 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]    164.855426 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]    169.359391 s: Service Status: DHCPC    : Enabled  : Fault    : 002
[IPU1-1]    200.656835 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]    200.956383 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]    230.057646 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]    230.357164 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]    260.258433 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]    260.657994 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]    310.359818 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]    310.559324 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]    339.560605 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]    339.660098 s:  NDK: Link Status: No Link on PHY 0
[IPU1-1]    370.361404 s:  NDK: Link Status: 10Mb/s Full Duplex on PHY 0
[IPU1-1]    370.560971 s:  NDK: Link Status: No Link on PHY 0

Please help to check, and guide me to completed the Network issue.

Widic

Part Number:66AK2L06

Hi,

We setup the boards by using the Optimized Radar System Design Using 66AK2L06 - DSP+ARM SoC and ADC14X250.

We were able to sample analog signal in high speed with 66AK2L EVM. 

We have achieved IQ Data (We get I and Q data separately) of input analog signal. (We used web interface to get I and Q datas)

But we could not understand what it means.. 

What is the relationship between IQ Data and real signal (Amplitude vs Time) ?

Thanks

Part Number:DRA74

Tool/software: TI-RTOS

If the invalid algorithm(for example x/0) effects share momery? we find the latency changed to longer, when running the invalid algorithm. Can you share us the document about this exception? Thanks a lot!

Part Number:AM6548

Tool/software: TI-RTOS

Hi

I am learning about the USB driver of AM6548,

and at this path : ti\pdk_am65xx_1_0_3\packages\ti\drv\usb\src\dwc

there are several files named with dwc

for example: usb_dwc_dcd.c

would you please tell me what does dwc means?

Best Regards

Part Number:AM4379

Tool/software: Linux

Hi,

I built a custom Linux kernel and rootfs by buildroot.

but it can't correctly receive the PRU interrupt.

I did copy the Linux kernel to the SD image you provided in Processor-SDK, and it works normal.

I also copy the kernel module form the SDK to my own image, and load them, the remoteproc is working, and I can tell the PRU to load the firmware and run it.

so, I came here for you support if there is any thing I missing for the configuration.

Thanks

Part Number:AM5746

Tool/software: TI-RTOS

Hello, TI Experts,

Our customer sent us questions about FATFS/MMCSD driver software in PROCESSOR-SDK-RTOS-AM57X.

Question:

- Could you tell us When/How to use "FATFS_defaultParams" in FATFS_drv.c?

- Could you tell us When/How to use "MMCSD_Params_init" in MMCSD_drv.c?

We would appreciate if you tell us the purpose and use-case of those functions.

Best regards,

Part Number:AM3357

Hi,

I try to get access to the boundary scan on a AM3357 device. The device runs fine in normal operation mode and access with JTAG and Code Composer Studio works fine as well.
When I try to access the boundary scan operation I get an error mesage from XJTAG software telling me that the JTAG chain is broken. With the same software I can access devices from the C2000 family without problems.
In a lot of different thread in E2E I can see that people have problems accessing boundary scan on Sitara devices. By the way: we have problems contacting a AM5716 as well.
It would help if an expert from TI could give a documenation on how boundary scan access has to be done. For example how to set signals like EMU0 and EMU1 while setting TRSTn high.

What about the pin "PMIC_POWER_EN" (C6). Does this pin stays in the same state when accessing boundary scan? (I think it is not controllable with boundary scan)

Any information on this topic is highly appreciated.

Thanks and best regards,

Patrick

Part Number:TDA2PXEVM

Tool/software: Linux

Hello,

After reboot,system will shut down every time.I recorded two logs, one is the system has just finished booting, the other is the system had run ten minutes.Could you help to have a look?

Thanks a lot 

Terence

(Please visit the site to view this file)

(Please visit the site to view this file)

Part Number:AM5728

Hello, TI Experts,

Our customer sent us device temperature related questions about AM5728.

Question:

   1: Are there any notice or recommendation about overheated risk by increasing leak current in higher temperature (Ta)?

   2: How do we have to care about device temperature variation if leak current increase?

   3: Are there any method to estimate the device temperature(Tj) such as below power estimation tool?  

https://training.ti.com/using-sitara-power-estimation-tool-5-minutes-or-less-0

We would appreciate if you tell us the recommended way or guide about overheated risk by increasing leak current in higher temperature.

Best regards,