Part Number:AM5728
what is the internal RAM in am5728.
I am willing to know the location of ROM code file with the Configuration of the device and initialization of primary peripherals in the code.
Is it possible to change these initializations by the user to create u-boot for custom hardware with am57xx processor.
my main goal is to create my own u boot and reduce the time to boot.
thanking you.
Part Number:TMDXEVM3358
Tool/software: Linux
Hi,
I have am335x GP EVM with ti-processor-sdk-linux-am335x-evm-04.02.00.09 SDK ported. I want to use DMTimer from userspace. I found dmtimer api in Linux/arch/arm/plat-omap/dmtimer.c and Linux/arch/arm/plat-omap/include/plat/dmtimer.h . When I tried to use any of dmtimer.c API from my code composure 7.0 application, its not compiling and gives dependency errors like *.h header file not found. I have included above two paths (Linux/arch/arm/plat-omap/ and Linux/arch/arm/plat-omap/include/plat/) in CCS but it keeps giving new header file dependencies. Please tell me how to compile dmtimer. from CCS.
Part Number:TDA3
Hi,
I am using TDA3xEVM. I want to flash images through UART using mflash utility. I am using Windows system.
But while building the mflash utility with command, gcc needs to be installed before.
gcc -o mflash mflash_uart.c
Can you recommend me a tested way in detail to make this setup for building mflash?
Part Number:XEVMK2LX
Hi Joe,
What is the DFE input rate limit for K2L processor. Will it support 30.72MHz?
I had sent a query
https://e2e.ti.com/support/processors/f/791/t/717739
For the same design, would like to know the Maximum and minimum supported data rate on DFE IQN2 side. Will it support 30.72MHz.
We are designing a LTE enodeB with 20MHz BW and 30.72MHz sampling rate.
But we are not sure whether DFE supports this low rate of 30.72MHz.
We are interfacing AFE7xxx for 4Tx4R configuration for LTE20. The AFE7xxx has 8 serdes JESD lanes. But K2L has 4 JESD Lanes.
The JESD lanes 5-8 on AFE7xxx is not used in the design.
Kindly advice the required sampling rates from AFE7xxx to DFE IQN2 for 4Tx4R LTE 20 MHz bandwidth. We are require to use 30.72MHz at DFE IQN2.
Kindly reply...
Regards,
Sumathi
Part Number:AM5728
Tool/software: Code Composer Studio
Hello,
I am working on a Sitara AM572x industrial EVM and I am developing a UART/DMA based communication channel between two different processor EVM. This has been successfully finalized so far. I was able to achieve my goals via enhancing the TI example project 'UART_BasicExample_idkAM572x_DMA_armTestproject'. Rahul helped me a lot in the past regarding this topic.
Afterwards I copied my code from the 'UART_BasicExample_idkAM572x_DMA_armTestproject' into another project, which is the project of the device that we are developing. This new project is derived from a GPIO example.
When trying to send data via the UART low level drivers, I call at the beginning the function 'UART_initConfig(true)' and this function calls as a result the function 'UartApp_edmaInit()'. I hit a breakpoint inside that function 'UartApp_edmaInit()' , see here:
The next instruction is a DMA library function 'edma3init' and calling this one leads to a termination of the program, see here:
The 'edma3init' function is a pre-compiled library so further debugging with the JTAG is not possible. I verified that the following lines are inside the *.cfg file:
var Edma = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
var drv = xdc.loadPackage ("ti.sdo.edma3.drv");
var rm = xdc.loadPackage ("ti.sdo.edma3.rm");
What can be the root cause that calling 'edma3init' is working on the 'UART_BasicExample_idkAM572x_DMA_armTestproject' but leads to a crash when being called out of our own project?
If there are too many potential causes for this behavior, how can I further debug the behavior and provide more specific information to you?
Kind regards,
Andreas
Part Number:TDA2EVM5777
Tool/software: TI C/C++ Compiler
HI,
i try to execute the ti board using NOR.i got message nor flash successfully done when i flash.i check with use case window appimage is not valid ,so please tell the solution for this.
Part Number:AM3359
Tool/software: Linux
Hardware:
HSR-network via:
1 Siemens Ruggedcom RS950G.
PC with windows 7 Pro SP1 license (pc), as the san-device connected via RJ45 cable into port "Local" of Siemens Ruggedcom RS950G.
1 AM3359 ICE 2.1 EVM on SDK 5.00.00.15 (sdk5) as HSR-device, communicated only by 1 patch cord RJ45 cable into port A or B.
The sceme of communication: PC <-> Siemens <-> AM3359.
Wireshark shows that sdk5 has stoped send the frames on arp-request (see atach "wireshark_ping_stoped.png").
But sdk3 (sd-card with image of sdk3, where no changes like the sdk5 ) always works fine.
So, according to wireshark:
- when AM3359 power is on, the ping-request from pc to sdk5 and ping-reply from sdk5 to pc is fine.
It works about ~1 minute than the ping is lost, and renews the same for a while every 10-30 minutes.
About the program code:
Frame analysis I did in module hsr_prp_forward.c in the procedure "void hsr_prp_forward_skb(struct sk_buff *skb, struct hsr_prp_port *port)".
Via printk I have print into the command line the data of skb. And this showed that the arp-request reaches the AM3359 finely (see atach "sdk5_reserved_arp.png", "sdk5_reserved_arp.png").
P.S. About "sdk5_reserved_arp.png": this screenshot is obtained when the cable disconnects from the AM3359 and connected in the pc with wireshark.
I understand from the fact that:
1. Sd-card with image of sdk3 works fine;
2. The frames are reaches the AM3359 finely;
- the bug is in sending the arp answer by sdk5.
And, I stood in a dead end. So I ask to understand it or at least to prompt what modules should be studied for the solution of this bug.
Part Number:TMS320C6418
Tool/software: Code Composer Studio
Hi there,
I'm developing an application with TMS320C6418, using CCS5.5.0
My configuration will use the external flash boot, but due to the 1K ROM boot limitation for this device I will need a second boot.
Looking at the "BlinkEVM6418" example I understand that with a boot.asm file I'm able to define an "User boot code" but something is not clear to me:
1) How is the "boot.asm" file added to the project? Do I simply add it as a file, or something needs to be changed on the project properties for the compilation?
2) Once the .out file is generated and the hex utility generates the .hex file, where do I have to store the file on the external flash? Does it have to be stored starting from the beginning of the external flash (EMIF CE1-> 0x9000 0000 - Flash address: 0x0000) or an offset of 1kbytes has to be considered (due to the 1k boot from ROM)?
3) Flash Burn plugin is considered on "BlinkEVM6418" example but I'm not able to find it, is it included on the CCS5 as a plugin?
Thank you
Regards
Karles
Part Number:LINUXEZSDK-SITARA
Tool/software: Linux
Hello together,
I’m running in an issue trying to access the pruss memory after a Linux kernel update from 3.12.31 to 4.9.98.
Memory access failed with a following bus error message from the OS.
I’ve read that this could be a clock issue, but the clocks are enabled. Further the CAN Intarfeces work fine.
Can anyone please help me?
Many Thanks in advance!
Here is the output:
#cat /sys/class/uio/uio0/maps/map0/addr
0x4a300000
# devmem2 0x4a300000
/dev/mem opened.
Memory mapped at address 0xb6f4a[84070.399007] Unhandled fault: external abort on non-linefetch (0x1018) at 0xb6f4a000
[84070.410656] pgd = eefac000
[84070.413509] [b6f4a000] *pgd=be922831
000.
[84070.422431] audit: type=1701 audit(1533278418.620:8): auid=4294967295 uid=0 gid=0 ses=4294967295 pid=262 comm="devmem2" exe="/usr/bin/devmem2" sig=7
Bus error (core dumped)
Part Number:TMS320C6748
We have developed a custom board with a C6748 processor. For now we've been developing in debug mode, but the idea is to load the code for an embedded W25Q80 SPI serial NOR flash, connected to SPI1 port, chip select 1.
The design is basded on the LCDK but several things change. We already made our custom GEL file for debugging and such. However, after reading documentation an guides I'm not 100% sure of the steps required to flash the app to the SPI flash.
For what I understand, I take the .out file generated while compiling the project and run it through AISgen. I have to configure AISgen for the particular ROM bootloader version in our chips (the latest) and also configure PLL's and DDR the same way I do in the GEL file. For what I understand, what AISgen does is take your executable image (.out) and add to it a header with instructions for the ROM bootloader to properly configure the required stuff before launching the app. Am I right?
Then it comes the flashing itself. Now for this I think there's two ways, with serial flasher or through CCS. I plan on using serial flasher. For that, I should configure the board for UART2 boot, launch the flasher utility with the correct settings and it should work. However, I read somewhere that I need to customize this serial flasher utility for custom boards, and that's where I get lost. Can you please guide me?
So far, I get the serial flasher to do something:
Attempting to connect to device COM6...
Press any key to end this program at any time.
(AIS Parse): Read magic word 0x41504954.
(AIS Parse): Waiting for BOOTME... (power on or reset target now)
(AIS Parse): BOOTME received!
(AIS Parse): Performing Start-Word Sync...
(AIS Parse): Performing Ping Opcode Sync...
(AIS Parse): Processing command 0: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 14112-Byte section to address 0x11800000.
(AIS Parse): Processing command 1: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 744-Byte section to address 0x11803720.
(AIS Parse): Processing command 2: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 32-Byte section to address 0x11803A28.
(AIS Parse): Processing command 3: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 20-Byte section to address 0x11803A48.
(AIS Parse): Processing command 4: 0x58535906.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Performing jump and close...
(AIS Parse): AIS complete. Jump to address 0x118031A0.
(AIS Parse): Waiting for DONE...
(AIS Parse): Boot completed successfully.
Waiting for SFT on the OMAP-L138...
Flashing application sh8test.bin (130032 bytes)
100% [ ████████████████████████████████████████████████████████████ ]
Image data transmitted over UART.however it gets stuck in there. I haven't modified the flash loader (using LCDK config).
Thanks,
David
Part Number:TMS320C6678
Tool/software: Code Composer Studio
Hi,
I'm working on a custom board in which C6678 is used.
I have included all the necessary files but i have getting the following errors.
Please help me how to proceed with this.
undefined first referenced
symbol in file
--------- ----------------
Convert_CoreLocal2GlobalAddr ./src/PM_dsp_Rresourcemgr.obj
HwiP_disable C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
HwiP_disableInterrupt C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
HwiP_enableInterrupt C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
HwiP_restore C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
NIMU_convertCoreLocal2GlobalAddr C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
NIMU_cppiGetPASSHandle C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
NIMU_getPAInstance C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
NIMU_osalRegisterInterruptDsp C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
NIMU_qmssGetFreeQ C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
NIMU_qmssQPushDescSize C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
NIMU_stopCppi C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
NIMU_stopQmss C:\ti\pdk_c667x_2_0_9\packages\ti\transport\ndk\nimu\lib\c6678\c66\release\ti.transport.ndk.nimu.ae66<nimu_eth.oe66>
Osal_qmssAccCsEnter C:\ti\pdk_c667x_2_0_9\packages\ti\drv\qmss\lib\c66\ti.drv.qmss.ae66<qmss_acc.oe66>
Osal_qmssAccCsExit C:\ti\pdk_c667x_2_0_9\packages\ti\drv\qmss\lib\c66\ti.drv.qmss.ae66<qmss_acc.oe66>
Osal_srioBeginMemAccess C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioCreateSem C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioEndMemAccess C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioEnterMultipleCoreCriticalSection C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioEnterSingleCoreCriticalSection C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioExitMultipleCoreCriticalSection C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioExitSingleCoreCriticalSection C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioFree C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioLog C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
Osal_srioMalloc C:\ti\pdk_c667x_2_0_9\packages\ti\drv\srio\lib\c66\ti.drv.srio.ae66<srio_drv.oe66>
platform_write ./src/PM_dsp_Rresourcemgr.obj
spi_claim ./src/PM_dsp_cmd_proc_module.obj
spi_release ./src/PM_dsp_cmd_proc_module.obj
spi_xfer ./src/PM_dsp_cmd_proc_module.obj
Awaiting for your Reply...!
Thanks & Regards,
Mounika Reddy
Part Number:AM5748
HI,
Presently I am working on a project which includes 2 processors, one is Sitara AM574x, another is from some other vendor, both the processors are connected through MII interface directly without any PHY IC, I need to establish a Ethernet communication between both processors with out a PHY chip, I found a document from TI forum which is attached with this post which suggests that this kind of point to point communication is possible, while I also found from the TI forums that this kind of communication is not possible as of in below link.
Please provide me clarity if it is possible or not? If possible to do this show me a path to go ahead.
Thanks,
Janardan M(Please visit the site to view this file)
Part Number:AM5726
Hello,
I want to use the LAN8710A phy IC on PRUSS MAC.
I had to use the MII interface to connect the PRUSS MAC with the phy. My problem is now, wath I have to do with the signal RP2_MII0_RXLINK and RP1_MII_RXLINK ?
You can see the connections:
Part Number:PROCESSOR-SDK-AM437X
Tool/software: Code Composer Studio
Hello,
I am trying to write to flash on the AM437x Industrial Development Kit.
I have access to the QSPI_BasicExample_idkAM437x_armExampleProject.
I have also integrated the spi_test() and spi_read_write() from the example.
Here is the problem: If this number is changed to anything below 64, it works. When this number is 64 or greater it fails.
void spi_test()
{
SPI_Params spiParams; /* SPI params structure */
S25FL_Handle flashHandle; /* Flash handle */
bool retVal = false; /* return value */
/* Init SPI driver */
SPI_init();
/* Default SPI configuration parameters */
SPI_Params_init(&spiParams);
/* Open QSPI driver */
flashHandle = SF25FL_open(((QSPI_INSTANCE - 1)+(QSPI_OFFSET)), &spiParams);
/* Print flash Id */
FlashPrintId(flashHandle);
/* Set the transfer length in number of 32 bit words */
transferLength = 50;
/* read/write test on block 0, address 0 */
retVal = spi_read_write(flashHandle, 0, transferLength);
if (retVal == true)
{
/* read/write test on block 256, address 16M */
retVal = spi_read_write(flashHandle, 256, transferLength);
}
SF25FL_close(flashHandle);
if(true == retVal)
{
DebugLog::Write("\n All tests have passed. \n");
}
else
{
DebugLog::Write("\n Some tests have failed. \n");
}
while(1);
}
I have narrowed it to failing at the highlighted line below in the function in the class S25FL.c: bool SF25FL_bufferWrite(S25FL_Handle flashHandle, S25FL_Transaction* flashTransaction)
if(QSPI_OPER_MODE_MMAP == object->qspiMode)
{
for(idx = 0; idx < length; idx++)
{
/* Write enable */
S25FLFlash_WriteEnable(flashHandle);
/* Perform the transfer */
transaction.txBuf = (unsigned char *)dstOffstAddr;
transaction.rxBuf = srcAddr;
transaction.count = 1;
transferType = SPI_TRANSACTION_TYPE_WRITE;
if (dstOffstAddr > 0xFFFFFFU)
{
transferCmd = QSPI_LIB_CMD_PAGE_PRG_4B;
}
else
{
transferCmd = QSPI_LIB_CMD_PAGE_PRG;
}
SPI_control(handle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
SPI_control(handle, SPI_V1_CMD_MMAP_TRANSFER_CMD, (void *)&transferCmd);
retVal = SPI_transfer(handle, &transaction);
/* Check flash status for completion */
while ((FlashStatus(flashHandle) & 0x1U));
dstOffstAddr += 1;
srcAddr += 1;
}
}Seeing as I am using example code, I am wondering why this is failing.
Any help would be greatly appreciated.
Part Number:AM3352
Tool/software: Linux
Hello,
In my kernel config file i have following paramter
CONFIG_ARM_APPENDED_DTB=y
CONFIG_INITRAMFS_SOURCE=rootfs.cpio
And while booting from u-boot I download my zImage image and .dtb file at two different memory location and use bootz XXXX - YYYY where
XXXXX - zImage address
YYYYY - dtb address
My question is - If I set CONFIG_ARM_APPENDED_DTB, in that case why do I have to download and specify dtb address to "bootz" command?
Do i have to make any changes in u-boot ? so it knows that dtb is already appended.
While building kernel - do I have to do any manual step to append DTB file?
Thanks,
NU
Part Number:AM3358
Tool/software: Linux
Hi Dear all,
I'm very new to processor and Yocto, I'm learning Yocto for my project by using "Using Yocto Project with BeagleBone Black" book.
I'm planning to use OSD3358-SM (I hope every one knows that this SIP uses AM3358)
In my board, I have I2c and IrDA communication. I plan to use UART1 of AM3358 will be both I2C and IrDA (TFDU4101)which required only two pins(Tx, Rx).
Is that possible or not, If yes kindly help me how to configure..
Please bear with me, if my English is not good.
Additional : I'm in schematic design phase
Thanks and regards
Part Number:AM3352
Tool/software: TI-RTOS
Is there a way to use the Starterware USB CDC driver to run USB in high-speed mode rather than full speed? If there is, I would have expected there to be something in the call to USBDCDCInit that would specify the USB speed. In particular, I would expect it to be in the psCDCDevice parameter which is of type tUSBDCDCDevice. The tUSBDCDCDevice struct does contain low level USB entries for USB Vendor and Product ID, maximum power and power attributes but I don't see anything that addresses the USB connection speed.
The Starterware Wiki 
has a table listing features where it says 'High Speed/Full Speed (Refer to Class Description for details)' in the columns for AM1808 and AM335X (I'm using AM3352 processor) in my application. But I've hit a dead end trying to find the 'Class Description' in order to find out how to select USB speed.
Kevin Jennings
Part Number:EVMK2H
Tool/software: TI C/C++ Compiler
Hello All.
Is there a way to clear out the memory when doing a soft reset? It seems some values get saved because when I load a new program the interrupts don't trigger unless I power cycle the board. is there something that i need to manage for this to not be an issue
Part Number:AM3358
hello,
The connection of DDR3 memory “MT41J-128M16-JT-125-IT-M” with the AM335x processor for data signals
If I swap a byte line as shown in the figure below, should I swap DQS and DQM as well?
Is there a way to use DQS and DQM without swap?
Regards,
Sohn
Tool/software: TI-RTOS
~/ti/processor_sdk_rtos_am57xx_4_00_00_04/demos/jailhouse-inmate/rtos$ ls
icss_emac pru-icss
i think this two jailhouse inmate rtos demo don't work normal.
Because i had test that the timer to call Clock_tick() don't work.
The timer don't interrupt running on jailhouse as inmate.
i want to know what should i do to make the rtos timer interrupt normal on jailhouse inmate.
Thanks.