L138 DSP I2C0 issue

Hi!

I try to use the I2C 0 on the DSP of the LCDK in polled mode and have some troubles with sending data.
I use CCS5.5, SYSBIOS 6.35.4.50, and I use CSL.
Yes I checked the code of the starterware demo (actually I used parts of it), but it is IRQ-based and I want to use polled IO.

The setup of the interface is performed as followed:

- 1. pinmux
- 2. bring i2c in reset mode
- 3. setup the clock (8MHz prescaled, 100kHz sclk)
- 4: clear int stat reg
- 5: ensure ICIVR is 0
- 6:  configure slave address
- 7: write the number of bytes to transfer in the data count register (2 here)
- 8. bring i2c up again

fine up to here.

the transmit routine is :

    //   1:  wait for bus free
    while ((i2cRegSet->ICSTR & CSL_I2C_ICSTR_BB_MASK) || !(i2cRegSet->ICSTR & CSL_I2C_ICSTR_ICXRDY_MASK));
 
    //   2:  set master mode and auto stop
    i2cRegSet->ICMDR = CSL_FMKT(I2C_ICMDR_MST,MASTER_MODE) //master mode
                               | CSL_FMKT(I2C_ICMDR_STP,SET) //enable autostop
                               | CSL_FMKT(I2C_ICMDR_STT,SET) //start
                               | CSL_FMKT(I2C_ICMDR_TRX,TX_MODE) //transmitter mode
                               | CSL_FMKT(I2C_ICMDR_IRS,ENABLE);  // keep enabled

     //   3:   write the regAddr of the slave devices to the TX register
    i2cRegSet->ICDXR = regAddr;

    //   4:   wait for the TX register to be free again
    while (!(i2cRegSet->ICSTR & CSL_I2C_ICSTR_ICXRDY_MASK));

    //   5:   write the data to the TX register
    i2cRegSet->ICDXR = regData;

    //   6:   wait for the transfer to end
    while (i2cRegSet->ICSTR & CSL_I2C_ICSTR_BB_MASK);

    //   7:   clear stop condition detected bit
    CSL_FINST(i2cRegSet->ICSTR,I2C_ICSTR_SCD,CLEAR);
-------------

This procedure works fine for the first use, but hangs at step 4 when transmitting the second pair of bytes.
When it hangs the reason seems to be that in the ICMDR register the MST and STP bits are 0 (STT still 1).

The procedure seems to work if there is a breakpoint or a wait loop at or before step 1, so I assume that there must be some timing issue.

Any suggestions?

Thanks,

Alex