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TMS320C6678: C66x DSP Cores - multicore DSP design

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Part Number:TMS320C6678

Hi there,

I am planning development for a Keystone I device as part of a larger project, and as somebody with very little DSP experience I am trying to wrap my head around how SYS/BIOS interacts with the DSP cores at a high level.

What I am trying to find out is if there is a way that SYS/BIOS can run across multiple (8) DSP cores, therefore using SYS/BIOS's scheduler to optimize tasking and usage of all the DSP cores. When I have played around with some of the Keystone I evaluation modules, I have seen that generally there is one .out file loaded onto each of the C66x DSP core. So how would I be able to get SYS/BIOS running on multiple cores, interacting with one another, with all processes being managed by a single scheduler? That way, the programmer (me) wouldn't need to write a scheduler by hand to optimize the use of all 8 C66x DSP cores (which is no easy task). Can this be done, or does one of the DSP cores need to be the master - tasking the other 7 cores using a custom scheduler?

I have seen some discussion of the Multicore Software Development Kit (MSDK) for SYS/BIOS, however this seems more geared towards a heterogeneous solution for the Keystone II where you have an ARM processor interacting with C66x DSP cores. I am not interested in interacting with an ARM processor, I need my implementation to run strictly on the C66x cores.

So ultimately the question is: how can I use SYS/BIOS to schedule jobs across all 8 of my Keystone C66x DSP cores?

Thanks,

Andre


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