thHi All,
I've encountered following issue:
McBSP is handled by DMA, HW FIFO for RX and TX is enabled because if disabled some samples were lost (there is only 2,5us to handle each sample and that's not enough when L138 is loaded). I'm using TI EDMA3 driver but our own McBSP driver.
McBSP FIFO in TX path can be controlled by WFIFOCTL register. It seems (it's not explicitly written) that field WNUMEVT controls the depth of the FIFO by defining event trigger condition. I've followed PSP example and said WNUMEVT to 1 although it was a bit strange to see that in PSP WNUMEVT is set to the value which is not defined in CSL
Mcbsp.c:
/* configure the transmit channel */
/* Step 1 : configure the "WNUMDMA" and "WNUMEVT" bits before *
* enabling the FIFO */
hMcbsp->fifoRegs->WFIFOCTL = (1 << CSL_BFIFO_WFIFOCTL_WNUMEVT_SHIFT);
cslr_mcbsp.h
#define CSL_BFIFO_WFIFOCTL_WNUMEVT_0WORDS (0x00000000u)
#define CSL_BFIFO_WFIFOCTL_WNUMEVT_4WORDS (0x00000004u)
#define CSL_BFIFO_WFIFOCTL_WNUMEVT_8WORDS (0x00000008u)
#define CSL_BFIFO_WFIFOCTL_WNUMEVT_12WORDS (0x0000000cu)
#define CSL_BFIFO_WFIFOCTL_WNUMEVT_16WORDS (0x00000010u)
Setting WNUMEVT=1 gives 64 words depth of FIFO. If I've tried to change WNUMEVT to different value McBSP is no longer triggering any events to DMA. I've tried to manipulate second WFIFO parameter WNUMDMA but I also didn't helped. It seems to me that the only acceptable configuration is WNUMEVT=1.
Am I doing something wrong or is it known/unknown HW issue?
For me, 64 words depth is much to deep since I want to update tx buffer on the fly. With such FIFO tx buffer updates are shifted out from McBSP 64 samples later - not acceptable latency.
Thanks in advance for any clue.