Part Number:AM5728
Tool/software: Linux
Hello Team,
Looking for some clarity on memory access in C66 DSP. We are using AM5728.
We are running the algorithm in DSP and allocated a buffer in CMEM pool. The CMEM pool is a memory pool in DDR that is configurable shareable between the A15 and the DSP
In the optimization process, when we copied the CMEM buffer to a separate DDR location, the cycle count is pretty good in compare to the cycle count seen in CMEM pool access. Why is that when both are in DDR?
Would you please explain? Are we missing something ?
As per the previous info from e2e forum, this pool alleviates the need to DMA between memories and CMEM pool access should not be expensive as it's cache based and used in video processing examples etc.
Looking forward to your prompt response. Thank you!
Best,
Rj