Part Number:AM5K2E04
Hello,
Investigating the initialization of DDR3 memory connected to a TI AM5K2E04, we observe the following behavior:
In conflict with the initialization procedure of DDR3 as defined in JEDEC Standard No. 79-3C, which says "After RESET# is de-asserted, wait for another 500 us until CKE becomes active", the DDRRESET# (pin D20) as well as the CKE signal (DDRCKE0, pin C20) provided by the AM5K2E04 both perform a rising edge about 5 ms after the rising edge of RESET of the AM5K2E04 (Pin AE29), with DDRCKE0 following DDRRESET# with a delay of only 15 ns.
About 600 ms later (!) we observe the "correct" initialization sequence in accordance with the JEDEC specification. This sequence can be traced back to the call of dram_init in U-Boot.
As the first release of the DDR RESET does not comply with the JEDEC Standard, we are concerned that this might lead to unintended behavior of the attached RAM and thus are seeking for a possibility to prevent the DDR Reset signal as provided by the AM5K2E04 from performing the "faulty" first rising edge.
Is there any possibility to modify the pin's behavior in this early stage after turning on the system?
In SPRS864D (p. 194) it says that "after the POR# pin is deasserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and remain in their reset state until otherwise configured by their respective peripheral"
Does this passage also apply to the DDR Reset pin and if so, can the mapping of the pin to a group be modified, thus getting a low state for DDRRESET#?
Thanks, best regards
Lennart