Part Number:AM5728
Tool/software: TI-RTOS
Hi,
On my device, in DSP1 core, I am trying to setup MCASP3 RX and TX in 32 bit, 8 slot TDM, sync mode with bit clock 24.576MHz / 96KHz frame sync (internal). DSP1 core (MCASP3) is setup as clock master for another external device.
- When I only configure TX for MCASP3, I am see audio data coming out from the MCASP3_AXR0 as expected, with no errors.
- When I enable RX, I see overrun error with unexpected frame sync error.
- The mcaspBindDev and mcaspCreateChan dont return any error.
- The callback passed to the mcaspCreateChan for MCASP3 RX is never being called by the driver.= after priming the RX and TX buffers.
- However, I do see callback happening for the TX
- I verified the pin mux/ pad IO setup
- The buffers are allocated on the L2SRAM
- I am aware of the errata i868, and have tried different values for the hwFifoEventDMARatio
The MCASP3 setup configuration is as follows -
{ /* MCASP3_TX */
0xFFFFFFFF, // MCASP_TXMASK
0x000080F0, // MCASP_TXFMT // Slot size = 32 bits, no bit delay
0x00000413, // MCASP_TXFMCTL
0x000000FF, // MCASP_TXTDM
0x0000000F, // MCASP_EVTCTLX
0x000001FF, // MCASP_TXSTAT
0x00000000, // MCASP_XEVTCTL
{
0x00000020, // MCASP_ACLKXCTL // CLKDIV = 1
0x0000800F, // MCASP_AHCLKXCTL // HDIV = 16
0x00000000 // MCASP_TXCLKCHK
}
},
{ /* MCASP3_RX */
0xFFFFFFFF, // MCASP_RXMASK
0x000080F0, // MCASP_RXFMT // Slot size = 32 bits, no bit delay
0x00000413, // MCASP_RXFMCTL
0x000000FF, // MCASP_RXTDM
0x0000000B, // MCASP_EVTCTLR
0x000001FF, // MCASP_RXSTAT
0x00000000, // MCASP_REVTCTL
{
0x00000020, // MCASP_ACLKRCTL // CLKDIV = 1
0x0000800F, // MCASP_AHCLKRCTL // HDIV = 16
0x00000000 // MCASP_RXCLKCHK
}
},
This is the dump of all status register using "omapconf dump mcasp3"
|--------------------------------------------|
| Reg. Name | Reg. Addr | Reg. Val. |
|--------------------------------------------|
| MCASP_PID | 0x48468000 | 0x44307B03 |
| PWRIDLESYSCONFIG | 0x48468004 | 0x00000001 |
| MCASP_PFUNC | 0x48468010 | 0x00000000 |
| MCASP_PDIR | 0x48468014 | 0xFC000001 |
| MCASP_PDOUT | 0x48468018 | 0x00000000 |
| MCASP_PDIN | 0x4846801C | 0x08000000 |
| MCASP_PDCLR | 0x48468020 | 0x00000000 |
| MCASP_GBLCTL | 0x48468044 | 0x0000031F |
| MCASP_AMUTE | 0x48468048 | 0x00000000 |
| MCASP_LBCTL | 0x4846804C | 0x00000000 |
| MCASP_TXDITCTL | 0x48468050 | 0x00000000 |
| MCASP_GBLCTLR | 0x48468060 | 0x0000031F |
| MCASP_RXMASK | 0x48468064 | 0xFFFFFFFF |
| MCASP_RXFMT | 0x48468068 | 0x000080F0 |
| MCASP_RXFMCTL | 0x4846806C | 0x00000413 |
| MCASP_ACLKRCTL | 0x48468070 | 0x00000020 |
| MCASP_AHCLKRCTL | 0x48468074 | 0x0000800F |
| MCASP_RXTDM | 0x48468078 | 0x000000FF |
| MCASP_EVTCTLR | 0x4846807C | 0x0000000B |
| MCASP_RXSTAT | 0x48468080 | 0x00000177 |
| MCASP_RXTDMSLOT | 0x48468084 | 0x00000000 |
| MCASP_RXCLKCHK | 0x48468088 | 0x00000000 |
| MCASP_REVTCTL | 0x4846808C | 0x00000000 |
| MCASP_GBLCTLX | 0x484680A0 | 0x0000031F |
| MCASP_TXMASK | 0x484680A4 | 0xFFFFFFFF |
| MCASP_TXFMT | 0x484680A8 | 0x000080F0 |
| MCASP_TXFMCTL | 0x484680AC | 0x00000413 |
| MCASP_ACLKXCTL | 0x484680B0 | 0x00000020 |
| MCASP_AHCLKXCTL | 0x484680B4 | 0x0000800F |
| MCASP_TXTDM | 0x484680B8 | 0x000000FF |
| MCASP_EVTCTLX | 0x484680BC | 0x0000000F |
| MCASP_TXSTAT | 0x484680C0 | 0x00000008 |
| MCASP_TXTDMSLOT | 0x484680C4 | 0x0000017F |
| MCASP_TXCLKCHK | 0x484680C8 | 0x56595300 |
| MCASP_XEVTCTL | 0x484680CC | 0x00000000 |
| MCASP_CLKADJEN | 0x484680D0 | 0x00000000 |
| MCASP_XRSRCTL0 | 0x48468180 | 0x00000011 |
| MCASP_XRSRCTL1 | 0x48468184 | 0x00000022 |
| MCASP_XRSRCTL2 | 0x48468188 | 0x00000000 |
| MCASP_XRSRCTL3 | 0x4846818C | 0x00000000 |
| MCASP_WFIFOCTL | 0x48469000 | 0x00000401 |
| MCASP_WFIFOSTS | 0x48469004 | 0x00000000 |
| MCASP_RFIFOCTL | 0x48469008 | 0x00010401 |
| MCASP_RFIFOSTS | 0x4846900C | 0x00000040 |
|--------------------------------------------|
And, omapconf show mcasp3 -
|---------------------------------------------|
| Data Ports and Buffers |
|---------------------------------------------|
| Port | DATA bus |
| Transmit DMA | |
| DMA request | Enabled |
| Status | No error |
| Receive DMA | |
| DMA request | Enabled |
| Status | No error |
| Transmit Buffer (XBUF) | |
| Status | No error |
| Receive Buffer (RBUF) | |
| Status | Overrun occurred |
| Write FIFO (WFIFO) | |
| State | Disabled |
| Threshold | 4 samples |
| Level | 0 samples in FIFO |
| Read FIFO (RFIFO) | |
| State | Enabled |
| Threshold | 4 samples |
| Level | 64 samples in FIFO |
|---------------------------------------------|
|----------------------------------------|
| Control |
|----------------------------------------|
| Transmit State-Machine | |
| State | Held in reset |
| Transmit Sequencer | |
| Enabled Slots | 8 |
| Active Slots | 8 |
| Active Slots Mask | 0x000000FF |
| Current Slot | Inactive |
| Receive State-Machine | |
| State | Active |
| Receive Sequencer | |
| Enabled Slots | 8 |
| Active Slots | 8 |
| Active Slots Mask | 0x000000FF |
| Current Slot | 0 |
|----------------------------------------|
|-----------------------------------------------------|
| Clocks |
|-----------------------------------------------------|
| Transmit Bit Clock | |
| State | Running |
| Divider | Divide-by 1 |
| Source | Internal |
| Polarity | Driven on rising edge |
| Transmit High-Speed Clock | |
| State | Running |
| Divider | Divide-by 16 |
| Source | Internal (AUXCLK) |
| Polarity | Non-inverted |
| Receive Bit Clock | |
| State | Running |
| Divider | Divide-by 1 |
| Source | Internal |
| Polarity | Samples on falling edge |
| Sync Mode | Synchronous to TX |
| Idle Mode | No-idle |
|-----------------------------------------------------|
|----------------------------------------------------|
| Frame Sync Generator |
|----------------------------------------------------|
| Transmit Frame Sync | |
| Generator State | Held in reset |
| Source | Internal |
| Polarity | Frame starts on falling edge |
| Pulse Width | Single word |
| Slot Count | 8 (TDM) |
| Data Delay | 0-bit |
| Status | No error |
| Receive Frame Sync | |
| Generator State | Active |
| Source | Internal |
| Polarity | Frame starts on falling edge |
| Pulse Width | Single word |
| Slot Count | 8 (TDM) |
| Data Delay | 0-bit |
| Status | Unexpected frame sync |
| Sync Mode | Synchronous to TX |
|----------------------------------------------------|
|----------------------------------------|
| Format Units |
|----------------------------------------|
| Transmit Format Unit | |
| Slot Size | 32 bits |
| Bit Mask | 0xFFFFFFFF |
| Padding | Pad with 0 |
| Right-Rotation | 0 bit positions |
| Bitstream Order | MSB first |
| Receive Format Unit | |
| Slot Size | 32 bits |
| Bit Mask | 0xFFFFFFFF |
| Padding | Pad with 0 |
| Right-Rotation | 0 bit positions |
| Bitstream Order | MSB first |
|----------------------------------------|
|---------------------------------|
| Serializers |
|---------------------------------|
| Transmit Serializers | Cleared |
| Receive Serializers | Active |
| Serializer 0 | |
| Mode | Transmit |
| Inactive State | Hi-Z |
| Serializer 1 | |
| Mode | Receive |
| Inactive State | Hi-Z |
| Serializer 2 | |
| Mode | Inactive |
| Inactive State | Hi-Z |
| Serializer 3 | |
| Mode | Inactive |
| Inactive State | Hi-Z |
|---------------------------------|
|--------------------------------------------|
| Pin Control |
|--------------------------------------------|
| AFSR | |
| Functionality | Receive Frame Sync |
| Direction | Output |
| ACLKR | |
| Functionality | Receive Bit Clock |
| Direction | Output |
| AFSX | |
| Functionality | Transmit Frame Sync |
| Direction | Output |
| ACLKX | |
| Functionality | Transmit Bit Clock |
| Direction | Output |
| AHCLKX | |
| Functionality | Transmit High-Freq Clock |
| Direction | Output |
| AXR0 | |
| Functionality | TX/RX Data Channel 0 |
| Direction | Output |
| AXR1 | |
| Functionality | TX/RX Data Channel 1 |
| Direction | Input |
| AXR2 | |
| Functionality | TX/RX Data Channel 2 |
| Direction | Input |
| AXR3 | |
| Functionality | TX/RX Data Channel 3 |
| Direction | Input |
|--------------------------------------------|