Hi All,
Note: We are using BIOS 5.33.05 / DSPLink 1.65.00.03 on the OMAP-L138 with Linux on the ARM Core.
Memory layout: Data/Program in DDR/L3 with L2/L1D/L1P caching enabled.
Clock Rate: DSP/ARM 456Mhz, eDMA 228Mhz
We are currently using the eDMA to ping-pong buffer and transport sets of data from the McASP FIFO into the internal L2 RAM. Furthermore, the eDMA is using Queue 0 along with TC0 which is set to a high priority in the SYSCFG module.
Now, we would like to further harness the eDMA power in order to reduce I/O constraints on our DSP. Therefore, we attempted to use another channel along with Queue 1 and TC1 for bulk data transfers from L2 into L3/DDR. However, it seems like the eDMA cannot guarantee our deadlines for transferring the bulk data into L3/DDR. Our deadline for the bulk transfer is 10msec for 12 kilobytes from L2 to either DDR or L3. Meaning we require ~9mbps throughput for the transfer which should be achievable given our clock rates.
If anyone could aid us in diagnosing this problem we would appreciate it
Thanks,
Arya B.