I make an ais file by using AISgen and hexAIS tools, The code generated by hexAIS can boot up and run the serial console correctly. But when I use AISgen to geneate the code, it boots up but the serial console seems running at a incorrect baud rate. Attached two jpg files showing the difference bwteen two generated files. Below is the cfg files for AISgen and hexAIS for reference.
AISgen cfg file:
Boot Mode=UART2
Boot Speed=115200
Flash Width=0
Flash Timing=3ffffffc
Configure Peripheral=True
Configure PLL0=True
Configure SDRAM=False
Configure PLL1=True
Configure DDR2=True
Configure LPSC=False
Configure Pinmux=False
Enable CRC=False
Specify Entrypoint=False
Enable Sequential Read=False
Use 4.5 Clock Divider=False
Use DDR2 Direct Clock=False
Use mDDR=True
ROM ID=0
Device Type=0
Input Clock Speed=24
Clock Type=0
PLL0 Pre Divider=1
PLL0 Multiplier=25
PLL0 Post Divider=2
PLL0 Div1=1
PLL0 Div3=3
PLL0 Div7=6
PLL1 Multiplier=25
PLL1 Post Divider=2
PLL1 Div1=1
PLL1 Div2=2
PLL1 Div3=3
Entrypoint=c1080000
SDRAM SDBCR=0
SDRAM SDTMR=0
SDRAM SDRSRPDEXIT=0
SDRAM SDRCR=0
DDR2 PHY=c4
DDR2 SDCR=a034622
DDR2 SDCR2=0
DDR2 SDTIMR=296b6458
DDR2 SDTIMR2=38232300
DDR2 SDRCR=924
LPSC0 Enable=
LPSC0 Disable=
LPSC0 SyncRst=
LPSC1 Enable=
LPSC1 Disable=
LPSC1 SyncRst=
Pinmux=4:220000+
App File String=C:\am1808_tools\u-boot;
AIS File Name=C:\am1808_tools\u-boot_uart_by_AISgen.ais
HexAIS ini file
; General settings that can be overwritten in the host code
; that calls the AISGen library.
[General]
; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
BootMode=UART
; NO_CRC,SECTION_CRC,SINGLE_CRC
crcCheckType=NO_CRC
[PLLANDCLOCKCONFIG]
PLL0CFG0 = 0x00180001
PLL0CFG1 = 0x00000205
PERIPHCLKCFG = 0x00000051
;********************************************************************************
;******************************* 150 MHz DDR settings ***************************
;********************************************************************************
; This section allows setting up the PLL1. Usually this will
; take place as part of the EMIF3a DDR setup. The format of
; the input args is as follows:
; |------24|------16|-------8|-------0|
; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
; PLL1CFG1: | RSVD | PLLDIV3|
[PLL1CONFIG]
PLL1CFG0 = 0x18010001
PLL1CFG1 = 0x00000002
; This section can be used to configure the PLL1 and the EMIF3a registers
; for starting the DDR2 interface on ARM-boot D800K002 devices.
; |------24|------16|-------8|-------0|
; DDRPHYC1R: | DDRPHYC1R |
; SDCR: | SDCR |
; SDTIMR: | SDTIMR |
; SDTIMR2: | SDTIMR2 |
; SDRCR: | SDRCR |
; CLK2XSRC: | CLK2XSRC |
[ARM_EMIF3DDR_PATCHFXN]
DDRPHYC1R = 0x000000C4
SDCR = 0x0A034622
SDTIMR = 0x1C912A08
SDTIMR2 = 0x3811C700
SDRCR = 0x00000494
CLK2XSRC = 0x00000000
[INPUTFILE]
FILENAME=u-boot.bin
LOADADDRESS=0xC1080000
ENTRYPOINTADDRESS=0xC1080000
A