Hi
I have some problems with our DMA configuration and do not understand how this can happen. There is the following scenario:
- DMA Queue/TC 0
- Gets events from UART 0 RX (Channel 8)
- UART Configured with 1.5 MBaud
- FIFO trigger level is 1
- Has Priority 0 configured in the MSTRPRI1 register
- Is linked to a PARAM Set so that a circular buffer can be realized
- Gets events from UART 0 RX (Channel 8)
- DMA Queue/TC 1
- Events are triggered manually (Channel 6)
- Has Priority 3 in the MSTRPRI1 register
- Transfers a big block of data from a FPGA
- the interface is slow (6MB/s)
- It is connected to EMIFA
- The burst size is 16 Byte
- The interface read rate is set to 32 Cycles (because it is slow)
System Configuration:
- Linux with a real time patch is used as operating system.
- A custom L137 board is used as Hardware Platform
- The SDRAM Memory is connected to EMIFB
The idea is that on each incoming package over UART the dma transfers the byte automatically into the memory (SDRAM). The UART Driver is working as expected as long as the second driver isn't loaded (The one which uses the DMA Queue 1). Then it happens relatively often that the FIFO is filled with more than one byte and no event is fired, so that the DMA stops working.
I can not understand how this can happen, because TC0 has the highest priority and as I've calculated a Byte over UART comes in every ~6us, a transfer of 16 Bytes from the FPGA takes around 2.56us, so the UART shouldn't miss any event.
Do I misunderstand something with the priorities and with the re arbitration of the system bus?
Is it possible for TC0 to access the SCR2 (Chapter 4.2 System Interconnect Block Diagram in the Technical Reference Manual) during the wait cycles of TC1?
Is there something else which should be configured to catch every event?
If this scenario isn't possible, is there a driver (For Linux or anther OS/bare), where the DMA together with the UART is used in RX direction?
Best regards,
Stefan