Part Number:AM3354
Hi team,
I am experiencing a problem with the USB0 port of one of my AM3354-based systems.
I am having trouble enumerating a cap touch controller board based on an Atmel cap touch controller IC. The controller board is from an outside vendor. Upon power up, the controller board does not enumerate, and the port shuts down, dropping Vbus. I receive a Babble interrupt when this happens. The problem doesn't always happen at the same point in the enumeration process. Sometimes no packets are exchanged, sometimes I see SOF packets, and sometimes I get all the way through to the first data exchange with SETUP packets transmitted and ACKd by the cap touch controller. Then the port shuts down.
Now, in the USB 2.0 specification, there is a time interval called out as Tsigatt, which is the maximum time from when Vbus is up to valid level to when a device has to signal attach. My cap touch board is a full speed device so it signals attach by driving D+ to the high state.
I have two cap touch boards that are used with this system. One is for an 8 in. LCD display and one is for a 10 in.
- The 8 in. controller always seems to enumerate successfully--it takes about 80 ms to drive D+ high following Vbus startup.
- The 10 in. controller takes from 100 ms to 103 ms. It rarely enumerates correctly--maybe 1 or 2 of ten tries. When it does enumerate successfully, it appears to continue to maintain valid communication.
- If I interpose an older USB 1.0 hub between the AM3354 port and my cap touch board, I see the hub driving D+ high very quickly after Vbus rises--within a ms. And the 10 inch cap touch board always works with this hub.
- When I view the D+ and D- signals, I don't see any signal integrity issues--noise is minimal and rise and fall times appear to be fine. I can decode the USB packets with their Tek scope, and they appear to be valid.
- I can plug a USB drive into the port and watch it setup a high speed connection--it always works fine.
Could this 100 ms timeout be the source of the problem? How is that time interval set within the AM3354 USB subsystem--is it register programmed, or set by the driver?
Going back to the spec, it says the Tsigatt time interval to be <100 ms for "all hub and device implementations". This is what I am concerned about. The spec is called out on Page 150 and shown in Figure 7-29 of the USB 2.0 Serial Bus Specification Revision 2.0.
Thanks,
Brian