I'm using omapl137, XDS510 USB emmulator and CCS5.
I downloaded the DSP and ARM gel file from http://support.spectrumdigital.com/boards/evmomapl137/revg/ 
and the following is some source code for clock and PLLC.
//-----------------------------------------------------------------------------
// helper function to initialize cpu, system, and pheripheral clocks.
// configure arm and dsp to 300 MHz and emif to 133MHz.
//-----------------------------------------------------------------------------
uint32_t init_clocks(void){
uint32_t rtn;
// unlock the system config registers.
SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;
//
rtn = config_pll0(0,24,1,0,0,2,7); //clkmode(internal), pllm, postdiv, plldiv1, plldiv2, plldiv3, plldiv7
//enable 4.5 divider PLL and set it as the EMIFA clock source.
SETBIT(SYSCONFIG->CFGCHIP[3], DIV4P5ENA | EMA_CLKSRC);
return (rtn);
}
uint32_t config_pll0(uint32_t clkmode, uint32_t pllm, uint32_t postdiv, uint32_t plldiv1, uint32_t plldiv2, uint32_t plldiv3, uint32_t plldiv7){
uint32_t i;
//-----------------------------------------------------------------------------
// A) Locking/Unlocking PLL Register Access
// 1. Write the correct key values to Kick0 and Kick1 registers.
// 2. Clear the PLL_MASTER_LOCK bit in CFGCHIP0.
// 3. Configure the desired PLLC register values.
// 4. Write an incorrect key value to the Kick registers.
//-----------------------------------------------------------------------------
// B) Initializing PLL Mode from PLL Power Down
// 1. Clear the PLLEN bit in PLLCTL to 0 (select PLL Bypass mode) and
// reset the PLL by clearing PLLRST bit in PLLCTL.
// Wait for 4 OSCIN cycles to ensure PLLC switches to bypass mode properly.
// refer) Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
// 2. Select the clock mode by programming the CLKMODE bit in PLLCTL.
// a) Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
// b) PLLCTL.EXTCLKSRC should be left to 0.
// 3. Clear the PLLRST bit in PLLCTL to 0 (reset PLL).
// 4. Clear the PLLPWRDN bit in PLLCTL to 0 to bring the PLL out of power-down mode.
// 5. Program the required multiplier value in PLLM.
// If desired to scale all the SYSCLK frequencies of a given PLLC,
// program the POSTDIV ratio.
// 6. If necessary, program PLLDIVn registers to change the SYSCLK0 to SYSCLKn divide values:
// a) Check for GOSTAT bit in PLLSTAT to clear to 0 to indicate that
// no GO operation is currently in progress.
// b) Program the RATIO field in PLLDIVx with the desired divide factors.
// c) Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
// d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).
// 7. Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset.
// 8. Wait for PLL to lock. See the device-specific data manual for PLL lock time.
// 9. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
//-----------------------------------------------------------------------------
// A-1. unlock the system config registers.
SYSCONFIG->KICKR[0] = KICK0R_UNLOCK; //0x83E70B13
SYSCONFIG->KICKR[1] = KICK1R_UNLOCK; //0x95A4F1E0
// A-2. unlock pll regs.
CLRBIT(SYSCONFIG->CFGCHIP[0], PLL0_MASTER_LOCK); //Bit4 in CFGCHIP0
// A-3. & B-1
// prepare to enable pll (PLLENSRC must be clear for PLLEN to have effect).
CLRBIT(PLL0->PLLCTL, PLLENSRC); //(adding -> exclusion??)
// switch to bypass mode & reset the PLL & wait 4 cycles to ensure it switches properly.
CLRBIT(PLL0->PLLCTL, PLLEN);
CLRBIT(PLL0->PLLCTL, PLLRST);
for (i = 0; i < 4; i++){}
// B-2. select clock mode (on-chip oscillator or external).
CLRBIT(PLL0->PLLCTL, PLLENSRC); //2-a)
CLRBIT(PLL0->PLLCTL, CLKMODE); //2-b)
SETBIT(PLL0->PLLCTL, (clkmode << CLKMODE_SHIFT));
// B-3. reset the pll.
CLRBIT(PLL0->PLLCTL, PLLRST);
// PLL initialization sequence
//----------------------------
// B-4. power up the pll...clear power down bit.
CLRBIT(PLL0->PLLCTL, PLLPWRDN);
/*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
for(i = 0; i < PLL_STABILIZATION_TIME; i++) {;} //exclusion??
// B-5. program the required multiplier value. & program postdiv ratio.
PLL0->PLLM = pllm; //l137_gel(input pllm = 24)
PLL0->POSTDIV = DIV_ENABLE | postdiv; //l137_gel(input postdiv= 1)
// B-6. a) spin until all transitions are complete.
while (CHKBIT(PLL0->PLLSTAT, GOSTAT)){}
// B-6. b) program the divisors.
PLL0->PLLDIV1 = DIV_ENABLE | plldiv1;
//PLL0->PLLDIV2 = DIV_ENABLE | plldiv2;
PLL0->PLLDIV3 = DIV_ENABLE | plldiv3; //l137_gel(input plldiv3 =2)
//PLL0->PLLDIV4 = DIV_ENABLE | (((plldiv1 + 1) * 4) - 1);
//PLL0->PLLDIV6 = DIV_ENABLE | plldiv1;
PLL0->PLLDIV7 = DIV_ENABLE | plldiv7; //l137_get(input plldiv7 = 7)
// B-6. c) kick off the transitions and spin until they are complete.
SETBIT(PLL0->PLLCMD, GOSET);
while (CHKBIT(PLL0->PLLSTAT, GOSTAT)){}
/*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
for(i = 0; i < PLL_RESET_TIME_CNT; i++) {;} /*128 MXI Cycles*/
// B-7. bring pll out of reset.
SETBIT(PLL0->PLLCTL, PLLRST);
//B-8. and wait for pll to lock.
for (i = 0; i < PLL_LOCK_CYCLES; i++) {}
// B-9. exit bypass mode.
SETBIT(PLL0->PLLCTL, PLLEN);
//A-4. lock pll regs.
SETBIT(SYSCONFIG->CFGCHIP[0], PLL0_MASTER_LOCK);
return (ERR_NO_ERROR);
Following is the source code of main.c
void main(){
int toggle_flag = 0;
#if NO_GEL
OMAPL137_init();
#endif
Init_Tim(); //setting and initializing
board_init(); //PINMUX defines
while(1)
{
if( toggle_flag == 0){
GPIO_setOutput(GPIO_BANK5, GPIO_PIN10, 1);
toggle_flag = 1;
}
else if( toggle_flag == 1){
GPIO_setOutput(GPIO_BANK5, GPIO_PIN10, 0);
toggle_flag = 0;
}
}
}
I measured the clock from an output(GPIO) by an oscilloscope.
The frequency was about 200KHz.
According the code, the code configured like this "arm and dsp to 300MHz and emif to 133MHz"
I wonder why the frequency that I measured is different from the code.
Do you have any idea to change the system clock?
Help me. PLEASE.
I really appreciate any help you can provide.