Has anyone seen data written into the DDR memory through the JTAG port being read back off by one address location with the beginning location in the burst being trashed? It’s as if the latencies between the DDR and AM1808 are off by one. We are loading code into the DDR through the JTAG when this happens.
It happens once in a while at power-up. Once the system is good it will stay good until a power cycle. The power sequencing is fine, per TI’s spec.
One time the board was left unpowered overnight and at the first power up the board had the problem. I’m pretty sure that overnight any locked up charges in the processor or DDR would have leaked away so it is not the type of hardware problem where a memory device like a register got locked into a bad setting at power off.
The DDR2 memory is running at about 150 MHz. It is 16 bits wide. The design has one DDR2 chip. The minimum speed of the DDR is 125 MHz. Maximum is 400 MHz. Multiple latencies are allowed, we’re in the middle and running so slow that all latencies are allowed. The processor is the AM1808 running at about 450 MHz.
Thanks
Steve