Hi,
We are trying to configure our custom board with OMAP L138 and Micron MT47H128M16RT DDR2 RAM. The Ram is a 128 Meg x 16 (16 Meg x 16 Bit x 8 banks) RAM. The RAM has a Timing – cycle time of 2.5ns @ CL = 5 (DDR2-800). The RAM has a page size of 1024.
We are able to run this configuration at a CPU clock of 300 MHz. MCLK was chosen at 150 MHz. We used OMAP-L1x/C674x/AM1x mDDR/DDR2 Memory Controller Register Setting Calculator for finding the register values required for this.
Now we want to run the CPU at its maximum frequency ie., @456MHz. We preserved the MCLK frequency at 150MHz. But we found that above a CPU clock of 360MHz, when we modify a RAM location the change is reflected. But data at multiple locations get corrupted.
Is there any dependency between VCLK and MCLK? As far as I understood from the datasheet and from various forum postings, there isn’t any dependency.
Also it is mentioned two bits, DDR_PDENA and CMOSEN in the DDR_SLEW register should be cleared for DDR2 operation. But in practical, we found that both need to be set for proper operation at 300 MHz.
Kindly help me to solve the issue.
Regards
Sreejaya