I have few quarries related to PCB layout using TI DSP TMS320C6746 and are mentioned below :
We are using three interfaces i.e HPI, Memory and MCBSP from DSP6746, and an external High speed Asynchronous SRAM of 256K x 16bits. The operating frequency for TMS320C6746 will be 400MHz and 100MHz for SRAM and HPI data. Number of PCB layers are four.
1. DSP and SRAM are placed on TOP side of PCB, half of SRAM address and data signals are routed on top and half on bottom side. TOP layer routed signals have adjacent layer GND and so GND reference, while bottom SRAM data and address signals have adjacent layer VCC and have 1.2V reference. So does it creates any problem if top and bottom layer same signals have different references ?
2. Similarly HPI Data signals are routed on TOP side and address on bottom, top side HPI data signals have GND reference while bottom side HPI address, CS-, WR- signals and MCBSP signals(STI, STO, C4 and FO-) have 3.3V reference(plane), so does it create any problem performance-wise ? if yes up-to what extent ?