Part Number:TDA2
Hello,
We're working with the TDA2x and currently using starterware_01_05_xx_xx. We want to configure the two A15 MMUs to manage different sections of DDR with different rules. Our goal is to have both A15 cores run in parallel and use cache for their instructions but not use cache for data. Both A15 cores can access each other's data space and so we want to disable cache for data spaces so that all updates are made directly to DDR. We understand this is achievable through the use of MMU descriptor tables.
If that's correct then we'd like to configure the MMU to place all instructions into one section of DDR and place all variables in other sections of DDR. We have examples available to us both in the latest PDK and older starterware examples but these examples only cover First-Level descriptor tables. Since these tables span a large range they don't provide the granularity to do what we need. Second-level descriptor tables seem to be what we need but we can't find any examples on how to program them using starterware or PDK functions. Can you provide any examples on how to achieve the following layout assignment for DDR?
0x8000.0000 - 0x85FF.FFFF - Instructions 1 for A15_0
0x8600.0000 - 0x86FF.FFFF - variable section 1 for A15_0
0x8700.0000 - 0x8AFF.FFFF - Instructions 2 for A15_1
0x8B00.0000 - 0x8FFF.FFFF - variable section 2 for A15_1
We're primarily working with starterware_01_05_xx_xx package and would prefer examples that use the functions available to that package. Any examples would be greatly appreciated.
Thank you.