Recently, we are working on a product enhancement project, the DSP processor is TMS320VC33, during debugging, we have found an issue.
We use a DMA interrupt to copy data from the serial port 0 of the DSP to implement analogue signal sampling.
The DMA length is set to 16.
We use two boards, one is responsible for analogue sampling and another is responsible for protection execution. The two boards use a sharedRAM to communicate. The sharedRAM is located in analogue sampling board.
But during implementation, we found that if the serial port data transfer clock rate is increased, for example, from 1.25Mhz to 2.5MHz, the data we have read from DMA dst address is wrong. And this error always occurred once the two boards write/read shardRAM.
So is there any link between sharedRAM access and serial port data transfer clock rate.
Can anyone give me some help? Thanks.