On a new hardware design we are seeing two WE pulses on the EMIFA within a single access. We are using a 25 MHz clock and the pulse widths behave as expected when the numbers are changed. We are trying to access a 16- bit NOR flash chip as an asynchronous memory.
The contents of the CEnCFG Register is 0x0812221D.
Data are correct on the first WE pulse but then goes to all zeroes for the second WE pulse.
Event timing is:
start CE: 0nsec
start first WE: 120 nsec (4 cyc)
end first WE: 200 nsec (2 cyc)
change address: 280 nsec (2 cyc)
start second WE: 360 nsec (2 cyc)
end second WE: 460 nsec (2 cyc)
end CE: 540 nsec (2 cyc)
(values in parentheses are incremental clock cycles).
Any help understanding this behavior would be appreciated.