Part Number:AM3359
I want to know how to restart McASP.
McASP works as Burst mode, uses Read FIFO and Write FIFO, and the data is transferred to and from the RAM by EDMA. Because the data transfer occurs intermittently, McASP and EDMA are restarted for each transfer, but it takes a lot of time. The current steps to restart are as follows:
/*
** Stop the data transmission
*/
/* Disable EDMA for the transfer */
EDMA3DisableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHANNEL_MCASP_TX, EDMA3_TRIG_MODE_EVENT);
/* Check if the Write FIFO is empty */
while(HWREG(MCASP_FIFO_REGS_BASEADDR + MCASP_FIFO_WFIFOSTS) & AFIFO_WFIFOSTS_WLVL) ;
/* Write FIFO is disabled, that is, the Write FIFO is flushed. */
HWREG(MCASP_FIFO_REGS_BASEADDR + MCASP_FIFO_WFIFOCTL) &= ~AFIFO_WFIFOCTL_WENA;
/* make sure that the WLVL field in the Write FIFO status register (WFIFOSTS)
** is reset to 0 and pointers are initialized,
*/
while(HWREG(MCASP_FIFO_REGS_BASEADDR + MCASP_FIFO_WFIFOSTS) & AFIFO_WFIFOSTS_WLVL) ;
/* Check if the transmit buffer is empty */
while(!(McASPTxStatusGet(MCASP_CTRL_REGS_BASEADDR) & MCASP_TX_STAT_DATAREADY) );
/* Wait until all data is shifted out from the AXRn and the transfer is completed */
SoftwareDelay(0);
/* Clears transmit serializers. The transmit buffer is flushed to an empty state. */
HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) &= ~MCASP_GBLCTL_XSRCLR;
while(HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) & MCASP_GBLCTL_XSRCLR) ;
/* Resets the Transmit State machine */
HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) &= ~MCASP_GBLCTL_XSMRST;
while(HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) & MCASP_GBLCTL_XSMRST) ;
/* Resets the Transmit frame sync generator */
HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) &= ~MCASP_GBLCTL_XFRST;
while(HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) & MCASP_GBLCTL_XFRST) ;
/*
** Stop the data reception
*/
/* Disable EDMA for the transfer */
EDMA3DisableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_MCASP_RX,
EDMA3_TRIG_MODE_EVENT);
/* Read FIFO is disabled, that is, the Read FIFO is flushed. */
HWREG(MCASP_FIFO_REGS_BASEADDR + MCASP_FIFO_RFIFOCTL) &= ~AFIFO_RFIFOCTL_RENA;
/* make sure that the RLVL bit in the Read FIFO status register (RFIFOSTS)
** is reset to 0 and pointers are initialized.
*/
while(HWREG(MCASP_FIFO_REGS_BASEADDR + MCASP_FIFO_RFIFOSTS) & AFIFO_RFIFOSTS_RLVL) ;
/* Clears receive serializers. The receive buffer is flushed.*/
HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) &= ~MCASP_GBLCTL_RSRCLR;
while(HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) & MCASP_GBLCTL_RSRCLR) ;
/* Resets the Receive State machine */
HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) &= ~MCASP_GBLCTL_RSMRST;
while(HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) & MCASP_GBLCTL_RSMRST) ;
/* Resets the Receive frame sync generator */
HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) &= ~MCASP_GBLCTL_RFRST;
while(HWREG(MCASP_CTRL_REGS_BASEADDR + MCASP_GBLCTL) & MCASP_GBLCTL_RFRST) ;
/*
** Restart the data reception
*/
/* Read FIFO is enabled. It must be enabled prior to taking McASP out of reset. */
HWREG(MCASP_FIFO_REGS_BASEADDR + MCASP_FIFO_RFIFOCTL) |= AFIFO_RFIFOCTL_RENA;
/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_MCASP_RX,
EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */
McASPRxSerActivate(MCASP_CTRL_REGS_BASEADDR);
/* Activate the state machines */
McASPRxEnable(MCASP_CTRL_REGS_BASEADDR);
/*
** Restart the data transmission
*/
/* Write FIFO is enabled. It must be enabled prior to taking McASP out of reset. */
HWREG(MCASP_FIFO_REGS_BASEADDR + MCASP_FIFO_WFIFOCTL) |= AFIFO_WFIFOCTL_WENA;
/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_MCASP_TX,
EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */
McASPTxSerActivate(MCASP_CTRL_REGS_BASEADDR);
/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(MCASP_CTRL_REGS_BASEADDR) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */
McASPTxEnable(MCASP_CTRL_REGS_BASEADDR);
What is the best procedure to restart?
The source code is attached. This is customized from the StarterWare of the old generation.
(Please visit the site to view this file)
Best regards,
Daisuke