RESETOUT deassertion to first instruction fetch from boot device

Question about the boot sequence on the OMAP L138.

Figure 5-4 on the datasheet shows that after a POR, RESETOUT gets deasserted 6169 cycles after RESET is deasserted and the boot pins latched.  On a warm boot, this delay is 4096 cycles.  In our system we connect RESETOUT to the reset pin of the SPI flash device used for boot.  So we need to be guaranteed that no instructions will get fetched during this delay, since the flash chip would still be in reset.  

• How does the L138 determine when to issue the first instruction fetch after RESETOUT is deasserted? 
• What is the internal clock configured when the device first comes up?
• How many cycles does it wait before it fetches the first instruction? 

Thanks,

Dinesh