Part Number:TMS320DM368
Hi,
We are using McBSP of DM368 as full duplex communication port in several of our custom boards, and it's configured as follows:
CLKX is generated by internal generator, clock frequency around 24MHz; Transmitting is carried out with EDMA; Frame pulses are generated by DXR copy.
CLKR and Receiving frame sync pulses are configured as input, and are generated by other devices; CLKR around 20 MHz. Interrupts and polling of SPCR RRDY bit are used for receiving data.
Transmitting and receiving are all configured in 32 bit modes.
McBSP works fine most of the time, but malfunctions randomly.
When malfunction happens, RRDY/RFULL bits in SPCR register remains high even after reading DRR register for several thousand times, which in normal condition requires no more than 2 ( Two 32bit register in RFULL condition).
Resetting RRST/XRST/GRST will temporarily clear RRDY/RFULL bits, but when new data is received and polling is started again, the module malfunctions immediately. Only complete resetting of whole SOC can return it to normal operation.
Probability of malfunction varies from board to board, though they have identical MCBSP and PLL settings.
Any idea how to avoid these malfunctions?