AM3358: PRU MII_RT configuration and registers

Part Number:AM3358

Hello,

I noticed in the pru-software-support-package include files that the am335x pru_cfg.h skips the MII_RT (event) field in the CFG register, while for example the am65x has the MII_RT field included.

I added it to my am335x pru_cfg.h and set the mii_rt event bit to 1:

CT_CFG.MII_RT_bit.MII_RT_EVENT_EN = 1; // Enable MII_RT mode

However, I also noticed that CCS 'skips' MII_RT in CFG

Same in the memory browser, but I see that the correct bit was set:

So my first question...  why is MII_RT skipped in the cfg file as well as in the CCS output, while it's implemented per AM335x TRM?

And my real question...  is it working? Is there a simple PRU code example that confirms how to setup the PRU MII_RT interface and verify it's working? I can'r see any data coming into R31...

My init code:

    /* Allow OCP master port access by the PRU so the PRU can read external memories */
    CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;


    // *** Start of PRU MII_RT setup ***
    CT_CFG.MII_RT_bit.MII_RT_EVENT_EN = 1; // Enable MII_RT mode
    CT_MII_RT.rxcfg0_bit.rx_mux_sel0 =  0;  // Receive data from MII RX Data from Port 0
    CT_MII_RT.rxcfg0_bit.rx_enable0 =   1;  // Enables the receive traffic selected by RX_MUX_SELECT
    // *** End of PRU MII__RT setup ***

Also the device tree has the MII_RT muxing for the PRU and the PRU is running and I can talk to it from Linux...