Hi
This question has been asked before but I cannot find a satisfactory answer on the forum.
What is the maximum skew between the DQS0 and DQS1 nets (and by definition, the corresponding routing classes)?
The OMAP-L138 mDDR routing requirements suggest that the length of the DQGATE trace should be equal to the sum of the clock trace and the average of the two DQS traces. I can hazard a guess that during a read, it enables OMAP to determine the earliest DQS and data will return after driving clock out.
But what happens when the lengths of these two DQS net classes diverge too far? It surely can't work with one group at 1 inch and another at 9", therefore there must be a limit?
I'm asking because we have a situation that looks like a byte lane (data + DQS0) is arriving too late, and this byte lane is the longer of the two. The DQGATE track length is nearer to the CK + DQS1 length than it is to the longer CK + DQS0 class. But this doesn't invalidate any of the routing constraints that I can find. Apologies if I missed one but it looks like others have asked this question, too.
<edited / corrected>
Thanks, Jon.