Hi,
we own a custom board with OMAPL138BZWT CPU with a 16bit NAND flash attached on EMIFA CS2. We had a working NAND flash / EDMA3 configuration for reading NAND as follows which we also used on OMAPL138LCDK for development.
We are using EDMA3_1 TC0 using QDMA.
In the data phase, while the ECC hw is active (between phases 1 and 3 of SPRUH77A in 'reads' section) the EDMA is configured as follows:
ACNT = 2
BCNT = 512 / 2
CCNT = 1
SBIDX=0
DBIDX=2
however, under this configuration the EMIF interface does not make read bursts on EMIFA interface (1 CE pulse / 1 read cycle).
We noticed that to enable bursts, we have to set SBIDX=ACNT, this way EDMA3 optimization on transfer will occur as staten in the EDMA3 documentation.
Under this new configuration we see 8 read pulses for every 1 CE cycle with a bandwidth good enough for our application. The problem is that with this new configuration (which only changes SBIDX) the ECC hardware always returns a syndrome value != 0 (ECC error indication). Where is the problem? Are there any issues related with 16 bit NAND flash or by this configuration?
Best regards,
Luca