Hi,
Now the EMIFA of DSP C6748 connects a 16 bit flash in our board for experiment. Our layout is based on the Figure
18-8(b) in Technical Reference Manual (SPRUH79A). The ASIZE field in CE2CFG register (0x68000010) is set to 1
for 16 bit data bus. However, the read/write test result is failed since the address mapping is incorrect in our Logic
Analyzer. Do we need to set another registers or hardware configuration? Any idea would be appreciated. Thank you.