AM1808: DDR2 TIMING Waveform

Part Number:AM1808

Hi,

When we have run the simulation on the DDR2 interface we are  seeing ringing on the Address lines which we are trying to address without adding the series resistance due to space constraints.

Is there a DDR2 timing waveform w.r.t AM1808 side across CK, Address, Data signals.  I have searched both the AM1808 datasheet as well as the Technical Reference manual but couldnot get the details.

Are is there any way to adjust the delay between the Clock and the Address signals. 

Regards,

Sudarshan