Part Number:PROCESSOR-SDK-OMAPL138
Tool/software: TI-RTOS
I use OMAPL138LCK.
I made LED blink code.
LED is blink at C6000 ccs 7.4 project. it works good.
LED is not blink at arm ccs 7.4 project. Code is Same,
I Used library of Processor-SDK-rtos-omapl138-lcdk.
Why does not work in Arm core.
--- code ---
/*****************************************************************************
** **
** main.c **
** by SJeong **
** **
*****************************************************************************/
#include <ti/csl/soc.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/cslr_syscfg.h>
#include <ti/csl/cslr_psc.h>
#include <ti/csl/cslr_pllc.h>
#include <ti/csl/cslr_gpio.h>
#include <ti/csl/cslr_uart.h>
#include <ti/csl/cslr_emif4f.h>
/*****************************************************************************
** **
** **
** **
*****************************************************************************/
// OMAPL1x SYSCFG Specific
#define KICK0_KEY 0x83E70B13u
#define KICK1_KEY 0x95A4F1E0u
#define KICK_LOCK 0x00000000u
/*****************************************************************************
** **
** **
** **
*****************************************************************************/
CSL_SyscfgRegsOvly sysRegs = (CSL_SyscfgRegsOvly) (CSL_SYSCFG_0_REGS);
CSL_PscRegsOvly psc0Regs = (CSL_PscRegsOvly) (CSL_PSC_0_REGS);
CSL_PscRegsOvly psc1Regs = (CSL_PscRegsOvly) (CSL_PSC_1_REGS);
CSL_PllcRegsOvly pll0Regs = (CSL_PllcRegsOvly) (CSL_PLLC_CFG_0_REGS);
CSL_PllcRegsOvly pll1Regs = (CSL_PllcRegsOvly) (CSL_PLLC_CFG_1_REGS);
volatile CSL_GpioRegs *gpioRegs = (CSL_GpioRegs *) (CSL_GPIO_0_REGS);
CSL_UartRegsOvly uartRegs = (CSL_UartRegsOvly) (CSL_UART_2_REGS);
CSL_UartRegsOvly uart0Regs = (CSL_UartRegsOvly) (CSL_UART_0_REGS);
CSL_UartRegsOvly uart1Regs = (CSL_UartRegsOvly) (CSL_UART_1_REGS);
CSL_UartRegsOvly uart2Regs = (CSL_UartRegsOvly) (CSL_UART_2_REGS);
CSL_EmifaRegsOvly emifaRegs = (CSL_EmifaRegsOvly) (CSL_EMIFA_0_REGS);
/*****************************************************************************
** **
** **
** **
*****************************************************************************/
#define BOARD_PINMUX0_GPIO_ENABLE (0x08000000u)
#define BOARD_PINMUX1_GPIO_ENABLE (0x08888000u)
#define BOARD_PINMUX5_GPIO_ENABLE (0x00008000u)
#define BOARD_PINMUX6_GPIO_ENABLE (0x00008880u)
#define BOARD_PINMUX13_GPIO_ENABLE (0x88888811u)
#define BOARD_PINMUX18_GPIO_ENABLE (0x80800000u)
void GpioPinMux(void)
{
//////////////////////////////////////////////
// D7: GPIO0[9]
// D4: GPIO6[13], D5: GPIO6[12]
/*
// GPIO0_9
sysRegs->PINMUX0 &= (~(CSL_SYSCFG_PINMUX0_PINMUX0_27_24_MASK));
sysRegs->PINMUX0 |= 0x08000000;
// GPIO6_12, GPIO6_13
sysRegs->PINMUX13 &= (~(CSL_SYSCFG_PINMUX13_PINMUX13_15_12_MASK |
CSL_SYSCFG_PINMUX13_PINMUX13_11_8_MASK));
sysRegs->PINMUX13 |= 0x00008800; // GPIO6[8:15]
*/
sysRegs->PINMUX0 &= (~(CSL_SYSCFG_PINMUX0_PINMUX0_27_24_MASK));
sysRegs->PINMUX0 |= BOARD_PINMUX0_GPIO_ENABLE;
sysRegs->PINMUX1 &= (~(CSL_SYSCFG_PINMUX1_PINMUX1_27_24_MASK |
CSL_SYSCFG_PINMUX1_PINMUX1_23_20_MASK |
CSL_SYSCFG_PINMUX1_PINMUX1_19_16_MASK |
CSL_SYSCFG_PINMUX1_PINMUX1_15_12_MASK));
sysRegs->PINMUX1 |= BOARD_PINMUX1_GPIO_ENABLE;
sysRegs->PINMUX5 &= (~(CSL_SYSCFG_PINMUX5_PINMUX5_15_12_MASK));
sysRegs->PINMUX5 |= BOARD_PINMUX5_GPIO_ENABLE;
sysRegs->PINMUX6 &= (~(CSL_SYSCFG_PINMUX6_PINMUX6_15_12_MASK |
CSL_SYSCFG_PINMUX6_PINMUX6_11_8_MASK |
CSL_SYSCFG_PINMUX6_PINMUX6_7_4_MASK));
sysRegs->PINMUX6 |= BOARD_PINMUX6_GPIO_ENABLE;
sysRegs->PINMUX13 &= (~(CSL_SYSCFG_PINMUX13_PINMUX13_31_28_MASK |
CSL_SYSCFG_PINMUX13_PINMUX13_27_24_MASK |
CSL_SYSCFG_PINMUX13_PINMUX13_23_20_MASK |
CSL_SYSCFG_PINMUX13_PINMUX13_19_16_MASK |
CSL_SYSCFG_PINMUX13_PINMUX13_15_12_MASK |
CSL_SYSCFG_PINMUX13_PINMUX13_11_8_MASK |
CSL_SYSCFG_PINMUX13_PINMUX13_7_4_MASK |
CSL_SYSCFG_PINMUX13_PINMUX13_3_0_MASK));
sysRegs->PINMUX13 |= BOARD_PINMUX13_GPIO_ENABLE;
sysRegs->PINMUX18 &= (~(CSL_SYSCFG_PINMUX18_PINMUX18_31_28_MASK |
CSL_SYSCFG_PINMUX18_PINMUX18_23_20_MASK));
sysRegs->PINMUX18 |= BOARD_PINMUX18_GPIO_ENABLE;
}
/*****************************************************************************
** **
** **
** **
*****************************************************************************/
void Init_Gpio()
{
// deassert GPIO local PSC reset and set NEXT state to ENABLE
psc1Regs->MDCTL[CSL_PSC_GPIO] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE ) | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
// move UART PSC to Next state
psc1Regs->PTCMD = CSL_FMKT( PSC_PTCMD_GO0, SET );
// wait for transition
while ( CSL_FEXT( psc1Regs->MDSTAT[CSL_PSC_GPIO], PSC_MDSTAT_STATE ) != CSL_PSC_MDSTAT_STATE_ENABLE );
// Set Direction (1:INPUT)
gpioRegs->BANK_REGISTERS[0].DIR = ~0x00000200;
gpioRegs->BANK_REGISTERS[3].DIR = ~0x00003000;
// clr Initial Data
gpioRegs->BANK_REGISTERS[0].CLR_DATA = 0x00000200;
gpioRegs->BANK_REGISTERS[3].CLR_DATA = 0x00003000;
}
/*****************************************************************************
** **
** **
** **
*****************************************************************************/
void SetupBasicComponents()
{
// dwPerm = MemoryProtect_MPPA_LOCAL | MemoryProtect_MPPA_SR | MemoryProtect_MPPA_SX | MemoryProtect_MPPA_UR | MemoryProtect_MPPA_UX;
// MemoryProtect_setPA((VOID*)0x10888000,(0x108e0000 - 0x10888000),dwPerm);
// Open Permissions to SYSCFG Registers
CSL_FINS(sysRegs->KICK0R, SYSCFG_KICK0R_KICK0, KICK0_KEY);
CSL_FINS(sysRegs->KICK1R, SYSCFG_KICK1R_KICK1, KICK1_KEY);
GpioPinMux();
Init_Gpio();
CSL_FINS(sysRegs->KICK0R, SYSCFG_KICK0R_KICK0, KICK_LOCK);
CSL_FINS(sysRegs->KICK1R, SYSCFG_KICK1R_KICK1, KICK_LOCK);
}
/*****************************************************************************
** **
** Main **
** **
*****************************************************************************/
Int main()
{
volatile int i;
SetupBasicComponents();
while(1) {
for (i = 0; i < 1000000; ++i ) ;
gpioRegs->BANK_REGISTERS[0].SET_DATA = 0x00000200;
for (i = 0; i < 1000000; ++i ) ;
gpioRegs->BANK_REGISTERS[0].CLR_DATA = 0x00000200;
}
;
return(0);
}