RTOS: Unable to change PPL1 settings on DSP OMAPL138 SoC

Tool/software:TI-RTOS

Hi there,

I have added the following PLL1 config function and for some reason it never gets completed. 

I am enable to change PLL0 config but not PLL1. 

Please, let me know if I am doing anything wrong in this function. Thanks. 

DSP_PLL1Init(24,1,0,1,2);

void DSP_PLL1Init( Uint8 pllm, Uint8 postdiv, Uint8 div1, Uint8 div2, Uint8 div3 )
{
// Clear PLL lock bit
syscfg_0_Regs->CFGCHIP3 &= ~(CSL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_MASK);

// Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR
pllc_1_Regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLENSRC_MASK;

// PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon
//pllc_1_Regs->PLLCTL &= ~CSL_PLLC_PLLCTL_EXTCLKSRC_MASK;

// Set PLLEN=0 to put in bypass mode
pllc_1_Regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLEN_MASK;

// wait for 4 cycles to allow PLLEN mux switches properly to bypass clock
sw_wait(4);

// Clear PLLRST bit to reset the PLL
pllc_1_Regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLRST_MASK;

// Disable the PLL output
//pllc_1_Regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLDIS_MASK;

// PLL initialization sequence
// Power up the PLL by setting PWRDN bit set to 0
//pllc_1_Regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLPWRDN_MASK;

// Enable the PLL output
//pllc_1_Regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLDIS_MASK;

// FIXME - how long?: Wait for the PLLs to stabilize - see PLL spec/datasheet
sw_wait(2000);

// Program the required multiplier value in PLLM
pllc_1_Regs->PLLM = pllm;

// If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio
pllc_1_Regs->POSTDIV = CSL_PLLC_POSTDIV_POSTDEN_MASK | postdiv;

// Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress
while (pllc_1_Regs->PLLSTAT & CSL_PLLC_PLLSTAT_GOSTAT_MASK);

// Program the RATIO field in PLLDIVx with the desired divide factors
pllc_1_Regs->PLLDIV1 = CSL_PLLC_PLLDIV1_D1EN_MASK | div1;
pllc_1_Regs->PLLDIV2 = CSL_PLLC_PLLDIV2_D2EN_MASK | div2;
pllc_1_Regs->PLLDIV3 = CSL_PLLC_PLLDIV3_D3EN_MASK | div3;

// Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition
pllc_1_Regs->PLLCMD |= CSL_PLLC_PLLCMD_GOSET_MASK;

// Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment)
while (pllc_1_Regs->PLLSTAT & CSL_PLLC_PLLSTAT_GOSTAT_MASK);

// FIXME: how long? Wait for PLL to reset - see PLL spec/datasheet
sw_wait(200);

// Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset
pllc_1_Regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLRST_MASK;

// Wait for PLL to lock. See PLL spec for PLL lock time
sw_wait(2000);

// Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode
pllc_1_Regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLEN_MASK;

// SET PLL lock bit
syscfg_0_Regs->CFGCHIP3 |= (0x1 << CSL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_SHIFT) & CSL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_MASK;

}
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