Hello TI,
I have been looking for memory protection mechanism for L1P, L1D and L2 memories. I know these memories can be configured partially as Memory or Cache, or fully as Memory or Cache. The mechanism for memory protection seems to be clear.
We use L1P and L1D configured fully as Caches and L2 configured fully as Memory, in our system.
I found that only "default" limitation for memory access exists for L1P. Does the following statement apply for both of configurations (for cache and for memory as well) ?
- The L1P regions can only be written to using EDMA or IDMA accesses; the L1P regions cannot be written to using CPU stores. The L1P regions can be read from using EDMA or IDMA accesses. CPU access is limited to instruction fetch. The CPU cannot read from L1P, even if L1P is memory-mapped. [DSP Megamodule ref sprufk5a.pdf, 2.3.1.2]
Or, is the access to L1P and L1D memories limited by another way when they are configured as caches? I mean, does it make even sense to configure memory protection for caches? I partially think that memory access to L1P and L1D caches is done through different bus (through cache controller) then when they're configured as memories.
Thank you for help
Best regards
Karel