Tool/software:TI-RTOS
Hi,
My projecy use OMAPL138. And it turn to deepsleep mode and wakeup ok. But when I replace normal OMAPL138 by secure OMAPL138, it cannot turn to deepsleep mode. The secure OMAP is unlocked and debug by jtag, but when turn to deepsleep, it stop at " while (pscstatus);"
Here is my code
uint32_t savePinMux;
uint32_t pscstatus;
uint32_t count;
// Unlock PLL configuration
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP0) &=
~SYSCFG_CFGCHIP0_PLL_MASTER_LOCK;
/* Clear PLL lock bit */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3) &=
~SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK;
// Config GP0[8] - DEEPSLEEP pin - pin number 9
// Ensure DEEPSLEEP pin is pinmux to DEEPSLEEP function
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0));
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = PINMUX0_31_28_DEEPSLEEP & \
savePinMux;
// Clear self refresh/low power (SR_PD) bit to 0
HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR) &= ~DDR2_MDDR_SDRCR_SR_PD;
// Set the low power mode enable
HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR) |= DDR2_MDDR_SDRCR_LPMODEN;
// Shut off MCLK by set MCLKSTOPEN to 1
HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR) |= DDR2_MDDR_SDRCR_MCLKSTOPEN;
// wait 150 CPU clock to allow MCLK to stop
for(count = 0; count < MCLK_STOP_TIME_DELAY; count++)
{
asm(" nop");
}
// Disable VCLK of SDRAM (For self-refresh mode)
// Turn off PSC for DDR2
// Wait for any previously initiated transitions
HWREG(SOC_PSC_1_REGS + PSC_MDCTL(HW_PSC_DDR2_MDDR)) = (PSC_MDCTL_NEXT_DISABLE & PSC_MDCTL_NEXT);
HWREG(SOC_PSC_1_REGS + PSC_PTCMD) = PSC_PTCMD_GO0;
do
{
pscstatus = HWREG(SOC_PSC_1_REGS + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT0;
}
while (pscstatus);
// Recheck status
pscstatus = PSC_MDCTL_NEXT_DISABLE & PSC_MDCTL_NEXT;
while ((HWREG(SOC_PSC_1_REGS + PSC_MDSTAT(HW_PSC_DDR2_MDDR)) & PSC_MDSTAT_STATE) != pscstatus);
/* PLLENSRC must be cleared before PLLEN bit have any effect */
HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLENSRC;
// PLLEN = 0 put pll in bypass mode in PLL0
HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLEN;
// Wait 4 cycle OSCIN
for(count = 0; count < PLLEN_MUX_SWITCH; count++)
{
asm(" nop");
}
// PLLPWRDN = 1 in PLL0
HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) |= PLLC_PLLCTL_PLLPWRDN;
/* PLLENSRC must be cleared before PLLEN has any effect*/
HWREG(SOC_PLLC_1_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLENSRC;
// PLLEN = 0 put pll in bypass mode in PLL1
HWREG(SOC_PLLC_1_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLEN;
// Wait 4 cycle OSCIN
for(count = 0; count < PLLEN_MUX_SWITCH; count++)
{
asm(" nop");
}
// PLLPWRDN = 1 in PLL1
HWREG(SOC_PLLC_1_REGS + PLLC_PLLCTL) |= PLLC_PLLCTL_PLLPWRDN;
// Config delay in the SLEEPCOUNT bit (ex: 0x0F)
HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_DEEPSLEEP) = \
((HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_DEEPSLEEP) &
~SYSCFG1_DEEPSLEEP_SLEEPCOUNT) | 0x000F);
// Set SLEEPENABLE bit in DEEPSLEEP to 1
HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_DEEPSLEEP)|=SYSCFG1_DEEPSLEEP_SLEEPENABLE;
// Polling bit SLEEPCOMPLETE
while (0 == (SYSCFG1_DEEPSLEEP_SLEEPCOMPLETE & HWREG(SOC_SYSCFG_1_REGS +
SYSCFG1_DEEPSLEEP)))
{
}
// Clear SLEEPENABLE bit in DEEPSLEEP to 0
HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_DEEPSLEEP) &= \
~SYSCFG1_DEEPSLEEP_SLEEPENABLE;
// Clear PLLRST bit in PLLCTL to 0
HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLRST;
// Clear PLLPWRDN bit in PLLCTL
HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLPWRDN;
// Set PLLRST bit in PLLCTL to 1 - out of reset
HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) |= PLLC_PLLCTL_PLLRST;
// Clear PLLRST bit in PLLCTL to 0
HWREG(SOC_PLLC_1_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLRST;
// Clear PLLPWRDN bit in PLLCTL
HWREG(SOC_PLLC_1_REGS + PLLC_PLLCTL) &= ~PLLC_PLLCTL_PLLPWRDN;
// Set PLLRST bit in PLLCTL to 1 - out of reset
HWREG(SOC_PLLC_1_REGS + PLLC_PLLCTL) |= PLLC_PLLCTL_PLLRST;
// Wait for PLL to lock
for(count = 0; count < PLL_LOCK_TIME_CNT; count++)
{
asm(" nop");
}
// Set the PLLEN bit in PLLCTL to 1 - remove bypass mode
HWREG(SOC_PLLC_0_REGS + PLLC_PLLCTL) |= PLLC_PLLCTL_PLLEN;
// Set the PLLEN bit in PLLCTL to 1 - remove bypass mode
HWREG(SOC_PLLC_1_REGS + PLLC_PLLCTL) |= PLLC_PLLCTL_PLLEN;
/* set PLL lock bit */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP0) |=
(0x01 << SYSCFG_CFGCHIP0_PLL_MASTER_LOCK_SHIFT )
& SYSCFG_CFGCHIP0_PLL_MASTER_LOCK ;
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3) &= CLK_PLL0_SYSCLK3;
/* set PLL lock bit */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3) |=
(0x1 << SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_SHIFT)
& SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK ;
// Enable VCLK of SDRAM
HWREG(SOC_PSC_1_REGS + PSC_MDCTL(HW_PSC_DDR2_MDDR)) = (PSC_MDCTL_NEXT_ENABLE & PSC_MDCTL_NEXT);
HWREG(SOC_PSC_1_REGS + PSC_PTCMD) = PSC_PTCMD_GO0;
do
{
pscstatus = HWREG(SOC_PSC_1_REGS + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT0;
}
while (pscstatus);
// Recheck status
pscstatus = PSC_MDCTL_NEXT_ENABLE & PSC_MDCTL_NEXT;
while ((HWREG(SOC_PSC_1_REGS + PSC_MDSTAT(HW_PSC_DDR2_MDDR)) & PSC_MDSTAT_STATE) != pscstatus);
// Set RESET_PHY bit in DDR PHY
HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDR_DRPYCRC) |= \
DDR2_MDDR_DRPYRCR_RESET_PHY;
while(DDR2_MDDR_DRPYRCR_RESET_PHY & \
HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDR_DRPYCRC));
// Clear MCLKSTOPEN bit in SDRCR
HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR) &= \
~DDR2_MDDR_SDRCR_MCLKSTOPEN;
// Disable Self refresh rate
// clear the low power mode
HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR) &= ~DDR2_MDDR_SDRCR_LPMODEN;Thanks,
Nhan