Part Number:OMAP-L138
Our application is programming uPPA and uPPB channels to receive periodically blocks of 4096 samples @ 1 msec rate.
The uPP configuration is dual channel Rx mode, 8-bit mode for uPPA, 16-bit mode for uPPB, Enable and Start signals enabled, Wait signal omitted, Clock signal is continuously generated by FPGA.
Even though the uPP peripheral was initialized following the step-by-step procedure described in the TI reference manual, unstable DMA transfers are observed over reset cycles such as either missing DMA transfer for one or both channels, or DMA transfer not synchronized between channels.
Is there any known issue on that topic? What kind of help TI can provide to help debugging the issue?
We found question related to providing uPP clocks during initialization sequence in https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/372349?tisearch=e2e-sitesearch&keymatch=upp%20clock
Could missing uPP clock signal during initialization cause similar issues to ours? (i.e unstable DMA transfers)
Note that we perform initialization of uPP peripheral according to step-by-step procedure (steps 1-7) during an application startup and programming of DMA transfer (steps 8-10) in the end of startup when everything should be prepared to start uPP receiving.