My customer has posed the following question:
This relates to interfacing TI DSPs to FPGAs using EMIF. We've done this a LOT in the past. Specifically, we've hooked up Altera Cyclone III, IV, V, Arria I and II.
My issue, specifically, is trying to understand the very high number of setup, and hold clocks that we have to configure to make it happy. I'm wondering if anyone has done this at TI and really optimized it. We currently have to run 3 setup, 3 hold and 3 strobe, for a total of 9 EMIF clocks per transaction. If we go below that, data integrity is lost. That has always seemed excessive to me, but in past designs, it was always fast enough. My current design (using the OMAPL138) is bringing in a LARGE amount of data, and a concern we have is that EMIF simply won't keep up when configured this way.
So, I'm hoping an FAE can tell us "Just flip this level, and it'll work" or "Do this and you'll get better throughput."
Is there someone who has experience with this that can provide some guidance?
Thanks.