PLL dividers in tms320c6745

Hi, 

I have a question related to the pll dividers. We want to use the DSP with a CLK frequency of 456 MHz (SYSCLK1 =456MHz) and i need too a SPI_CLOCK frequency of approximately 27 MHz (SYSCLK2 = 27MHz). I have seen on the tms320c6745 datasheet http://www.ti.com/lit/ug/spruh91d/spruh91d.pdf (page 118)  this:

"The divide values in PLL controller 0 for SYSCLK1/SYSCLK6, SYSCLK2, and SYSCLK4 are not fixed
so that you can change the divide values for power saving reasons. But you are responsible to assure
that the divide ratios between these clock domains must be fixed to 1:2:4."

Therefore  if I can only use that values i can't reach the frequency value that I need. So can I use other values to get the frequency that I need or not?

Thank you very much.