For correct operation, must UHPI_HAS during UHPI_HSTROBE inactive cycle be kept High?
Our customer uses C6746 with AM3359. UHPI_HAS connects to GPMC_ADVn_ALE. UHPI_HAS during UHPI_HSTROBE inactive cycle is not kept High.
The write access after the read access fails then some data buses show the middle level voltages.
Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs) (Rev. F)
http://www.ti.com/lit/ds/sprs717f/sprs717f.pdf
Figure 5-26. GPMC and Multiplexed NOR Flash - Asynchronous Read - Single Word
Figure 5-27. GPMC and Multiplexed NOR Flash - Asynchronous Write - Single Word
When UHPI_HAS is controlled by GPMC_ADVn_ALE configured as a GPIO.
If UHPI_HAS during UHPI_HSTROBE inactive cycle is not kept High, this issue occurs.
If UHPI_HAS during UHPI_HSTROBE inactive cycle is kept High, this issue does not occur.
Best regards,
Daisuke