Quantcast
Channel: Processors forum - Recent Threads
Viewing all articles
Browse latest Browse all 17527

Compiler: TI v8.1.2

$
0
0

Tool/software: TI C/C++ Compiler

Hello,

We are working on an LCDK-OMAPl138 platform with ARM920 and C6000 cores. 

We build images for both ARM and DSP. The  Firmware running on ARM gets a DSP binary image that we created using AISGen.

Following the description in "OMAP-L138 C6000 DSP+ARM Processor Technical Reference Manual"  - "13.2 DSP Wake Up" we load this image

to 0xc3000000 and issue the gel file procedure Wake_DSP() which is listed at the bottom of my question. 

The entrypoint location is at 0xC3000000: Below is the message frm the map file:

ENTRY POINT SYMBOL: "_c_int00"  address: c3000000

Howwever, the DSP is not automatically connected, so we can't use it this way- though the wake up succeeded.

While trying to use CCV to download the elf image and connect - it works fine. But this is not what we need.

The memory contents of 0xC3000000 created while using CCV to upload the elf file look quite different that the image created by AISgen.

Questions:

1-Is AISgen the right tool to create a binary for C6000?  What is wrong with the image creation? (And yes, I used the DSP creation option)

2-Is there any HW procedure I missed? (please refer to the Wake_DSP()  code?

3-Where can I see how CCV translates the out file?

Thank you all,

Please let me know if you need more information on this.

/*PSC0_LPSC_enableCore(1, LPSC_DSP)*/

PSC0_LPSC_enableCore(unsigned int PD, unsigned int LPSC_num) {
unsigned int j;

if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x11F) != 0x103 ) {
HOST1CFG = 0xc3000000;
*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFEE0) | 0x0103;
PSC0_PTCMD = 0x1<<PD;
j = 0;
/*Wait for power state transition to finish*/
while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) {
if( j++ > PSC_TIMEOUT ) {
GEL_TextOut("\tPSC0 Enable Core Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
break;
}
}

j = 0;
while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x11F) !=0x103) {
if( j++ > PSC_TIMEOUT ) {
GEL_TextOut("\tPSC0 Enable Core Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
break;
}
}
}
}


Viewing all articles
Browse latest Browse all 17527

Trending Articles