Part Number:OMAP-L138
Team: OMAP L138 i2c. data Technical user guide http://www.ti.com/lit/ug/spruh77c/spruh77c.pdf
Page 1031, bit 5 IRS. States, if reset bit in ICMDR is set during a transfer it can cause i2c bus to hang. If this should happen, how do you "unhang" the bus?
Regards,
Naser
Page 1031, bit 5 IRS.
“5 IRS I2C reset bit. Note that if IRS is reset during a transfer, it can cause the I2C bus to hang (I2Cx_SDA and I2Cx_SCL are in a high-impedance state).
0 The I2C is in reset/disabled. When this bit is cleared to 0, all status bits (in ICSTR) are set to their default values.
1 The I2C is enabled.”