Part Number:TMS320C6748
Tool/software: Code Composer Studio
Hai,
I am facing problem in #41 error in spi header file what ever i2c defined same thing defined in spi also errors occurring in struture of spi header file.
/*
* spi.h
*
* Created on: DEC 4, 2016
*
*/
#ifndef SPI_H_
#define SPI_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "types.h"
struct SPIGCR0_BITS {
uint32_t RESET:1; // 0 SPI is out of Reset state
uint32_t rsvd1:31; // 31:1 reserved
};
union SPIGCR0_REG {
uint32_t all;
struct SPIGCR0_BITS bit;
};
struct SPIGCR1_BITS {
uint32_t SETMASTER:2; // 1:0 0 SLAVE MODE,3h MASTER MODE
uint32_t rsvd1:6; // 7:2 reserved
uint32_t POWERDOWN:1; // 8 1 The SPI is in power-down mode,0 The SPI is in active mode.
uint32_t rsvd2:7; // 15:9 reserved
uint32_t LOOPBACK:1; // 16 1 Internal loop-back test mode enabled.,0 Internal loop-back test mode disabled.
uint32_t rsvd3:7; // 23:17 reserved
uint32_t ENABLE:1; // 24 1 Activates SPI.,0 SPI is not activated for transfers.
uint32_t rsvd4:7; // 31:25 reserved
};
union SPIGCR1_REG {
uint32_t all;
struct SPIGCR1_BITS bit;
};
struct SPIINT_BITS {
uint32_t DLENERRENA:1; // 0 Enables an interrupt when data length error occurs.
uint32_t TIMEOUTENA:1; // 1 Enables an interrupt on a time-out of the SPIx_ENA signal.
uint32_t PARERRENA:1; // 2 Enables an interrupt on a parity error.
uint32_t DESYNCENA:1; // 3 Enables an interrupt on desynchronization of the slave.
uint32_t BITERRENA:1; // 4 Enables an interrupt on a bit error.
uint32_t rsvd1:1; // 5 reserved
uint32_t OVRNINTENA:1; // 6 Overrun interrupt will be generated.
uint32_t rsvd2:1; // 7 reserved
uint32_t RXINTENA:1; // 8 Interrupt will be generated.
uint32_t TXINTENA:1; // 9 Interrupt will be generated upon SPIFLG.TXINTFLG being set to 1.
uint32_t rsvd3:6; // 15:10 reserved
uint32_t DMAREQEN:1; // 16 DMA requests will be generated.
uint32_t rsvd4:1; // 23:17 reserved
uint32_t ENABLEHIGHZ:1; // 24 SPIx_ENA pin remains in high-impedance when not active.
uint32_t rsvd5:1; // 31:25 reserved
};
union SPIINT_REG {
uint32_t all;
struct SPIINT_BITS bit;
};
struct SPILVL_BITS {
uint32_t DLENERRLVL:1; // 0 An interrupt on data length error is mapped to interrupt line INT1.
uint32_t TIMEOUTLVL:1; // 1 An interrupt on a time-out of the SPIx_ENA signal is mapped to interrupt line INT1.
uint32_t PARERRLVL:1; // 2 A parity error interrupt is mapped to interrupt line INT1.
uint32_t DESYNCLVL:1; // 3 An interrupt due to desynchronization of the slave is mapped to interrupt line INT1.
uint32_t BITERRLVL:1; // 4 Bit error interrupt is mapped to interrupt line INT1.
uint32_t rsvd1:1; // 5 reserved
uint32_t OVRNINTLVL:1; // 6 Receive overrun interrupt is mapped to interrupt line INT1.
uint32_t rsvd2:1; // 7 reserved
uint32_t RXINTLVL:1; // 8 Receive interrupt is mapped to interrupt line INT1.
uint32_t TXINTLVL:1; // 9 Transmit interrupt is mapped to interrupt line INT1.
uint32_t rsvd3:6; // 31:10 reserved
};
union SPILVL_REG {
uint32_t all;
struct SPILVL_BITS bit;
};
struct SPIFLG_BITS {
uint32_t DLENERRFLG:1; // 0 A data length error has occurred.
uint32_t TIMEOUTFLG:1; // 1 An SPIx_ENA signal time-out occurred.
uint32_t PARERRFLG:1; // 2 A parity error occurred.
uint32_t DESYNCFLG:1; // 3 Slave is desynchronized
uint32_t BITERRFLG:1; // 4 A bit error occurred.
uint32_t rsvd1:1; // 5 reserved
uint32_t OVRNINTFLG:1; // 6 Overrun condition has occurred.
uint32_t rsvd2:1; // 7 reserved
uint32_t RXINTFLG:1; // 8 A newly received data is ready to be read. Receive buffer is full.
uint32_t TXINTFLG:1; // 9 Transmit buffer is empty. An interrupt is pending to fill the transmitter.
uint32_t rsvd3:6; // 31:10 reserved
};
union SPIFLG_REG {
uint32_t all;
struct SPIFLG_BITS bit;
};
struct SPIPC0_BITS {
uint32_t SCS0FUN:8; // 7:0 SPIx_SCS[n] pin is a SPI functional pin.
uint32_t ENAFUN:1; // 8 SPIx_ENA pin is a SPI functional pin.
uint32_t CLKFUN:1; // 9 SPIx_CLK pin is a SPI functional pin.
uint32_t SIMOFUN:1; // 10 SPIx_SIMO pin is a SPI functional pin.
uint32_t SOMIFUN:1; // 11 SPIx_SOMI pin is a SPI functional pin.
uint32_t rsvd1:1; // 31:12 reserved
};
union SPIPC0_REG {
uint32_t all;
struct SPIPC0_BITS bit;
};
struct SPIDAT1_BITS {
uint32_t TXDATA:16; // 15:0 SPIGCR1.ENABLE must be set to 1 before this register can be written to. Writing a 0 to the
uint32_t CSNR:8; // 23:16 SPIx_SCS[n] pin is driven high.
uint32_t DFSEL:2; // 25:24 Data word format 3 is selected
uint32_t WDEL:1; // 26 After a transaction, SPIFMTn.WDELAY of the selected data format
uint32_t rsvd1:1; // 27 reserved
uint32_t CSHOLD:1; // 28 The chip select signal is held active at the end of a transfer
uint32_t rsvd2:3; // 31:29 reserved
};
union SPIDAT1_REG {
uint32_t all;
struct SPIDAT1_BITS bit;
};
struct SPIBUF_BITS {
uint32_t RXDATA:16; // 15:0 SPI receive data. This is the received data, transferred from the receive shift-register
uint32_t rsvd1:8; // 23:16 reserved
uint32_t DLENERR:1; // 24 A data length error has occurred.
uint32_t TIMEOUT:1; // 25 An SPIx_ENA signal time-out occurred.
uint32_t PARERR:1; // 26 A parity error occurred.
uint32_t DESYNC:1; // 27 A slave device is desynchronized.
uint32_t BITERR:1; // 28 A bit error occurred.
uint32_t TXFULL:1; // 29 The transmit buffer is full; SPIDAT0/SPIDAT1 is not ready to accept new data.
uint32_t RXOVR:1; // 30 A receive data overrun condition occurred since last time reading the data field.
uint32_t RXEMPTY:1; // 31 No data received since last reading of the SPIBUF register.
};
union SPIBUF_REG {
uint32_t all;
struct SPIBUF_BITS bit;
};
struct SPIDELAY_BITS {
uint32_t C2EDELAY:8; // 7:0 SPI receive data. This is the received data, transferred from the receive shift-register
uint32_t T2EDELAY:8; // 15:8 reserved
uint32_t T2CDELAY:8; // 23:16 A data length error has occurred.
uint32_t C2TDELAY:8; // 31:24 An SPIx_ENA signal time-out occurred.
};
union SPIDELAY_REG {
uint32_t all;
struct SPIDELAY_BITS bit;
};
struct SPIDEF_BITS {
uint32_t CSDEF:8; // 7:0 SPI receive data. This is the received data, transferred from the receive shift-register
uint32_t rsvd1:24; // 31:8 reserved
};
union SPIDEF_REG {
uint32_t all;
struct SPIDEF_BITS bit;
};
struct SPIFMT0_BITS {
uint32_t CHARLEN:5; // 4:0 SPI data word length. Legal values are 2h
uint32_t rsvd1:3; // 7:5 reserved
uint32_t PRESCALE:8; // 15:8 SPI clock frequency = SPI module clock/(PRESCALE + 1)
uint32_t PHASE:1; // 16 SPI clock signal is delayed by a half SPI clock cycle versus the transmit/receive data stream.
uint32_t POLARITY:1; // 17 SPI clock signal is high-inactive (before and after data transfer the clock signal is high).
uint32_t DISCSTIMERS:1; // 18 No C2TDELAY or T2CDELAY is inserted in the chip select timings.
uint32_t rsvd2:1; // 19 reserved
uint32_t SHIFTDIR:1; // 20 Least significant bit is shifted out first.
uint32_t WAITENA:1; // 21 Before the SPI starts the data transfer it waits for the SPIx_ENA signal
uint32_t PARENA:1; // 22 A parity is transmitted at the end of each transmit data stream.
uint32_t PARPOL:1; // 23 An odd parity flag is added at the end of the transmit data stream.
uint32_t WDELAY:6; // 29:24 WDELAY × PSPI module clock + 2 × PSPI module clock PSPI module clock -> Period of SPI module clock
uint32_t rsvd3:2; // 31:30 reserved
};
union SPIFMT0_REG {
uint32_t all;
struct SPIFMT0_BITS bit;
};
//-----------------------------------------------------------------------------
// Register Structure & Defines
//-----------------------------------------------------------------------------
struct SPI_REGS
{
volatile union SPIGCR0_REG SPIGCR0; // 0x0000 (SPI Global Control Register 0)
volatile union SPIGCR1_REG SPIGCR1; // 0x0004 (SPI Global Control Register 1)
volatile union SPIINT_REG SPIINT; // 0x0008 (SPI Interrupt Register)
volatile union SPILVL_REG SPILVL; // 0x000C (SPI Interrupt Level Register)
volatile union SPIFLG_REG SPIFLG; // 0x0010 (SPI Flag Register)
volatile union SPIPC0_REG SPIPC0; // 0x0014 (SPI Pin Control Register 0 (Function))
volatile uint32_t SPIPC1; // 0x0018 (SPI Pin Control Register 1 (Direction))
volatile uint32_t SPIPC2; // 0x001C (SPI Pin Control Register 2 (Input))
volatile uint32_t SPIPC3; // 0x0020 (SPI Pin Control Register 3 (Output))
volatile uint32_t SPIPC4; // 0x0024 (SPI Pin Control Register 4 (Set SPIPC3))
volatile uint32_t SPIPC5; // 0x0028 (SPI Pin Control Register 5 (Clear SPIPC3))
volatile uint32_t RSVD0[3]; // 0x002C
volatile uint32_t SPIDAT0; // 0x0038 (SPI Data Transmit Register 0)
volatile union SPIDAT1_REG SPIDAT1; // 0x003C (SPI Data Transmit Register 1)
volatile union SPIBUF_REG SPIBUF; // 0x0040 (SPI Receive Buffer Register)
volatile uint32_t SPIEMU; // 0x0044 (SPI Receive Emulation Register)
volatile union SPIDELAY_REG SPIDELAY; // 0x0048 (SPI Delay Register)
volatile union SPIDEF_REG SPIDEF; // 0x004C (SPI Default Chip Select Register)
volatile union SPIFMT0_REG SPIFMT0; // 0x0050 (SPI Data Format Register 0)
volatile uint32_t SPIFMT1; // 0x0054 (SPI Data Format Register 1)
volatile uint32_t SPIFMT2; // 0x0058 (SPI Data Format Register 2)
volatile uint32_t SPIFMT3; // 0x005C (SPI Data Format Register 3)
volatile uint32_t INTVEC0; // 0x0060 (SPI Interrupt Vector Register 0)
volatile uint32_t INTVEC1; // 0x0064 (SPI Interrupt Vector Register 1)
};
//---------------------------------------------------------------------------
// SPI External References & Function Declarations:
//
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif /* SPI_H_ */
Description Resource Path Location Type for Errors
#41 expected an identifier c6748_spi.h /LEDTest line 22 C/C++ Problem
#41 expected an identifier c6748_spi.h /LEDTest line 37 C/C++ Problem
#41 expected an identifier c6748_spi.h /LEDTest line 134 C/C++ Problem
#41 expected an identifier c6748_spi.h /LEDTest line 136 C/C++ Problem
#41 expected an identifier c6748_spi.h /LEDTest line 153 C/C++ Problem