Hello,
I'm currently using the EDMA3 controller on the OMAP L138 (running at 456MHz) for 16-bit transfers to and from the SPI0 peripheral. The SPI0 peripheral is set up as a slave on the L138 and is being driving at almost 25MHz SPI clock rate (so about 750 ns per 16-bit transfer). The DMA transfers in and out are double buffered using EDMA3 Paramsets. Memory used for the transfers is L2 (IRAM).
To minimize issues with SPI transfers, I've dedicated transfer controller 0 of channel controller 0 to the SPI0 peripheral by setting the SPI events to go to queue zero. All other peripherals using DMA uses TC1 (via queue 1).
I've also changed the master priority registers (in the SYSCFG module) to let EDMA3_0_TC0 run at priority 0 (default). EDMA3_0_TC1 runs at priority 1 (changed from default) and EDMA3_1_TC0 runs at priority 4 (default).
Unfortunately, I'm sometimes still seeing a dropped 16-bit word. Can anyone advise what other optimizations or changes are needed to run the SPI peripheral at the datasheet speed of 25MHz?
Thanks