OMAP-L138 uPP transaction hangs

I have AD9361 connected to OMAP-L138 via uPP port in full duplex mode, RX_CLK is 31 MHz, UPP_2xTXCLK sourced with 62 MHz, thus TX_CLK is 31 MHz too. Physically routed clock, data and enable lines, start and wait are not used.

The problem is:

1) I see some tx transactions successful after start (amplitude modulation at AD9361 output is visible by spectrum analyser), but then it stops at while (CSL_FEXT(uppRegs->UPIS2, UPP_UPIS2_PEND)); and UORI at UPISR is high.
What may be the reason? Clock is too slow compared to maximum 75 MHz allowed.

2) The memory at recv_buffer is unchanged, no any data.


My code here:

  // Reset the module
    reg = uppRegs->UPPCR;
    CSL_FINST(reg, UPP_UPPCR_SWRST, RESET);
    i = 2000; while (--i);
    CSL_FINST(reg, UPP_UPPCR_SWRST, RUNNING);
    uppRegs->UPPCR = reg;

    // Full duplex, A - TX, B - RX
    reg = uppRegs->UPCTL;
    CSL_FINST(reg, UPP_UPCTL_MODE, DUPLEX1);
    CSL_FINST(reg, UPP_UPCTL_CHN, TWO);

    // DDR, 12 bit data width
    CSL_FINST(reg, UPP_UPCTL_DRA, DOUBLE);
    CSL_FINST(reg, UPP_UPCTL_IWA, 16BIT);
    CSL_FINST(reg, UPP_UPCTL_DPWA, 12BIT);
    CSL_FINST(reg, UPP_UPCTL_DRB, DOUBLE);
    CSL_FINST(reg, UPP_UPCTL_IWB, 16BIT);
    CSL_FINST(reg, UPP_UPCTL_DPWB, 12BIT);
    uppRegs->UPCTL = reg;

    // Start/enable pins settings
    reg = uppRegs->UPICR;
    CSL_FINST(reg, UPP_UPICR_STARTA, DISABLE);
    CSL_FINST(reg, UPP_UPICR_ENAA, ENABLE);
    CSL_FINST(reg, UPP_UPICR_STARTB, DISABLE);
    CSL_FINST(reg, UPP_UPICR_ENAB, ENABLE);
    uppRegs->UPICR = reg;

    // Idle value
    reg = uppRegs->UPIVR;
    CSL_FINS(reg, UPP_UPIVR_VALA, 0xFFFF);    // TODO
    CSL_FINS(reg, UPP_UPIVR_VALB, 0xFFFFu);
    uppRegs->UPIVR = reg;

    // Enable uPP
    reg = uppRegs->UPPCR;
    CSL_FINST(reg, UPP_UPPCR_EN, ENABLE);
    CSL_FINST(reg, UPP_UPPCR_RTEMU, ENABLE);
    CSL_FINST(reg, UPP_UPPCR_SOFT, ENABLE);
    uppRegs->UPPCR = reg;

    for (i = 0; i < 64; i++)
        recv_buffer[i] = -1;

    while (1) {
        //
        System_printf(" --- Generating sine wave ---\n");
        for (i = 1; i < 1464843; i++) {

            uppRegs->UPID0 = (Uint32)&xmit_buffer;
            uppRegs->UPID1 = (1 << 16)|128;        // 1 lines 128 bytes per line
            uppRegs->UPID2 = 128;                                        // no offset between lines

            while (CSL_FEXT(uppRegs->UPIS2, UPP_UPIS2_PEND));
        }

        System_printf(" --- Collecting 64 samples from ADC --- \n");

        uppRegs->UPQD0 = (Uint32)&recv_buffer;
        uppRegs->UPQD1 = (1 << 16)|128;        // 1 lines 128 bytes per line
        uppRegs->UPQD2 = 128;                                        // no offset between lines

        while (CSL_FEXT(uppRegs->UPQS2, UPP_UPQS2_PEND));

        for (i = 0; i < 64; i += 2)
            System_printf("%d %d\n", recv_buffer[i], recv_buffer[i+1]);

    }