All:
CCS 6.1.1
Starterware_1_10_04_01
I am working with a target which has 50 MHz input clock, and the following is done to get PLL0 and PLL1 working:
#define PLL_CLK_SRC 1
#define PLL0_MUL 26 // for 337.5 MHz.
#define PLL0_PREDIV 3 // for 337.5 MHz.
#define PLL0_POSTDIV 0
#define PLL0_DIV1 0
#define PLL0_DIV3 2
#define PLL0_DIV7 6
I found a problem with InitPLL0() - if DIV1 is zero, then the derived values for DIV2, DIV4, and DIV6 are also zero.
I made a change to allow for DIV2 to be 1, which resulted in 168.75 MHz.
When in emulation mode, I can get SPI0 to work - I am able to run at 18.75 MHz.
(By the way, SPI1 is set for 150 MHz, and can run with no problem at 25 MHz.)
However, when I try standalone mode, SPI0 does not get interrupts, and if I comment out the code that deals with setting up and running SPI0, the SPI1 runs fine.
I am scratching my head, trying to find the problem, but I also wanted to post in case someone else has dealt with this!